- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullNone
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,2 @@
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "embedded_kcpsm3.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn embedded_kcpsm3.prj
|
||||
-ifmt mixed
|
||||
-ofn embedded_kcpsm3
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top embedded_kcpsm3
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso embedded_kcpsm3.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/Assembler/INT_TEST.VHD"
|
||||
vhdl work "kcpsm3_int_test.vhd"
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn kcpsm3_int_test.prj
|
||||
-ifmt mixed
|
||||
-ofn kcpsm3_int_test
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top kcpsm3_int_test
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso kcpsm3_int_test.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1,40 @@
|
||||
#
|
||||
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
|
||||
# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
|
||||
# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
|
||||
# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
|
||||
# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
|
||||
# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
|
||||
# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
|
||||
# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
|
||||
# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
|
||||
# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
|
||||
# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
|
||||
# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE.
|
||||
#
|
||||
# (c) Copyright 2005 Xilinx, Inc.
|
||||
# All rights reserved.
|
||||
#
|
||||
|
||||
# Bus clock nets
|
||||
NET sys_clk_in TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TSSYSCLK" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
|
||||
|
||||
NET sys_clk_in LOC = AE14;
|
||||
NET sys_clk_in IOSTANDARD = LVCMOS33;
|
||||
NET sys_rst_in LOC = D6;
|
||||
NET sys_rst_in PULLUP;
|
||||
NET sys_rst_in TIG;
|
||||
|
||||
NET sys_rx LOC = W2;
|
||||
NET sys_rx IOSTANDARD = LVCMOS33;
|
||||
NET sys_rx TIG;
|
||||
NET sys_tx LOC = W1;
|
||||
NET sys_tx IOSTANDARD = LVCMOS33;
|
||||
NET sys_tx TIG;
|
||||
|
||||
NET sys_alarm LOC = G5; #GPLED0
|
||||
NET sys_alarm TIG;
|
||||
NET sys_alarm SLEW = SLOW;
|
||||
NET sys_alarm DRIVE = 2;
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Oct 01 18:35:41 Westeuropäische Sommerzeit 2005
|
||||
##
|
||||
vlib work
|
||||
vcom -93 -explicit kcpsm3.vhd
|
||||
vcom -93 -explicit ./Assembler/INT_TEST.VHD
|
||||
vcom -93 -explicit kcpsm3_int_test.vhd
|
||||
vcom -93 -explicit test_bench.vhd
|
||||
vsim -t 1ps -lib work testbench
|
||||
do {testbench.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 1000ns
|
||||
@@ -0,0 +1,15 @@
|
||||
## NOTE: Do not edit this file.
|
||||
## Auto generated by Project Navigator for Post-PAR Simulation
|
||||
##
|
||||
vlib work
|
||||
## Compile Post-PAR Model
|
||||
vcom -explicit -93 "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.vhd"
|
||||
vcom -explicit -93 "test_bench.vhd"
|
||||
vsim -t 1ps -sdfmax /UUT=E:/work/VHDL/XilinxISE/Projects/PicoBlaze/netgen/par/kcpsm3_int_test_timesim.sdf -lib work testbench
|
||||
do {testbench.udo}
|
||||
view wave
|
||||
add wave *
|
||||
view structure
|
||||
view signals
|
||||
run 10us
|
||||
## End
|
||||
@@ -0,0 +1,4 @@
|
||||
-- ProjNav VHDL simulation template: testbench.udo
|
||||
-- You may edit this file after the line that starts with
|
||||
-- '-- START' to customize your simulation
|
||||
-- START user-defined simulation commands
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,8 @@
|
||||
vhdl work "kcuart_tx.vhd"
|
||||
vhdl work "kcuart_rx.vhd"
|
||||
vhdl work "bbfifo_16x8.vhd"
|
||||
vhdl work "uart_tx.vhd"
|
||||
vhdl work "uart_rx.vhd"
|
||||
vhdl work "kcpsm3.vhd"
|
||||
vhdl work "E:/work/VHDL/XilinxISE/Projects/PicoBlaze/Assembler/UCLOCK.VHD"
|
||||
vhdl work "uart_clock.vhd"
|
||||
@@ -0,0 +1,4 @@
|
||||
NET "sys_clk_in" TNM_NET = "sys_clk_in";
|
||||
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 10 ns HIGH 50 %;
|
||||
OFFSET = IN 8 ns BEFORE "sys_clk_in" ;
|
||||
OFFSET = OUT 12 ns AFTER "sys_clk_in" ;
|
||||
@@ -0,0 +1,34 @@
|
||||
|
||||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:4
|
||||
-g CclkPin:PullUp
|
||||
-g M0Pin:PullUp
|
||||
-g M1Pin:PullUp
|
||||
-g M2Pin:PullUp
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g InitPin:Pullup
|
||||
-g CsPin:Pullup
|
||||
-g DinPin:Pullup
|
||||
-g BusyPin:Pullup
|
||||
-g RdWrPin:Pullup
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullNone
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutDown:Disable
|
||||
-g DCIUpdateMode:AsRequired
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:No
|
||||
-g DriveDone:No
|
||||
-g Encrypt:No
|
||||
@@ -0,0 +1,55 @@
|
||||
set -tmpdir ./xst/projnav.tmp
|
||||
set -xsthdpdir ./xst
|
||||
run
|
||||
-ifn uart_clock.prj
|
||||
-ifmt mixed
|
||||
-ofn uart_clock
|
||||
-ofmt NGC
|
||||
-p xc4vsx35-10-ff668
|
||||
-top uart_clock
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-lso uart_clock.lso
|
||||
-keep_hierarchy NO
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case maintain
|
||||
-slice_utilization_ratio 100
|
||||
-dsp_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style lut
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract YES
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-mux_extract YES
|
||||
-resource_sharing YES
|
||||
-use_dsp48 auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 32
|
||||
-bufr 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Auto
|
||||
-use_sync_set Auto
|
||||
-use_sync_reset Auto
|
||||
-iob auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
@@ -0,0 +1 @@
|
||||
work
|
||||
@@ -0,0 +1,3 @@
|
||||
vhdl work "kcuart_rx.vhd"
|
||||
vhdl work "bbfifo_16x8.vhd"
|
||||
vhdl work "uart_rx.vhd"
|
||||
Reference in New Issue
Block a user