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UART9 readme.txt
Please open this file in Notepad or WordPad or use a non proportional font for best display format.
9-Bit UART Macros with Integral FIFO Buffers.
Suitable for communication with Parity.
Release 1 - 3rd March 2005
Author
------
Ken Chapman
Staff Engineer - Spartan Applications Specialist
Xilinx Ltd (UK)
email: ken.chapman@xilinx.com
Introduction
------------
These macros have been supplied to complement the standard 8-bit UART macros supplied with PicoBlaze.
You are advised to look at the standard macros and documentation (UART_manual.pdf) first as these
variants take almost the same format and must be used and controlled in the same fundamental way.
The UART9 macros provide a UART which has 1 start bit, 9 data bits and 1 stop bit.
The additional data bit can be used to provide different functionality depending on the way you
choose to interpret it.
Transmitter macro is called 'uart9_tx.vhd' and the additional bit is data_in(8).
Receiver macro is called 'uart9_rx.vhd' and the additional bit is data_out(8).
Parity - Drive data_in(8) with a High or Low depending on the state or the remaining data bits
data_in(7 downto 0) and the desired ODD or EVEN parity.
Interpret and check the received data_out(8) as required by your application.
Data - The additional bit can be used as an additional data bit.
Stop bit - Forcing a High and checking for High allows the UART to provide 1 start bit, 8 data
bits and 2 stop bits format.
Is Parity Required?
-------------------
The most common reason for the 9th bit is to provide support for parity. Before choosing to
implement parity in a system you should ask the fundamental question "Do I really need it?".
To help answer that question, you need to consider what your system will do if a parity error
should occur. Will it just ignore an error and what will be the effect if it does? If it
does not ignore the error, then what will it do? All of these factors will need to be solved
at a higher level than these macros and PicoBlaze will almost certainly provide a suitable
platform in which to implement this protocol.
In many cases the need for parity is simply to enable connection to another piece of equipment
which expects parity and which can not be changed. It is not unusual in these cases for the received
parity to be ignored or for incorrect data to be discarded with unpredictable results. Fortunately
most serial connections such as RS232 are now very reliable once initial communication has
been established.
Using the Macros
----------------
The macros are provided as source VHDL and should be instantiated in your design. Each macro
also uses two sub macros and therefore these files must also be added to the project.
uart9_tx
|
|__kcuart9_tx
|
|__bbfifo_16x9
uart9_rx
|
|__kcuart9_rx
|
|__bbfifo_16x9
The instantiation templates are exactly the same as those required for the standard 8-bit
macros except that the data bus in each case is now 9 bits.
Component declaration........
----------------------------------------------------------------------------------------
component uart9_tx
Port ( data_in : in std_logic_vector(8 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
component uart9_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(8 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
----------------------------------------------------------------------------------------
Component Instantiation......
Signal names will probably change to fit with your design.
----------------------------------------------------------------------------------------
transmit: uart9_tx
port map ( data_in => data_in,
write_buffer => write_buffer,
reset_buffer => reset_buffer,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
buffer_full => buffer_full,
buffer_half_full => buffer_half_full,
clk => clk );
receive: uart9_rx
port map ( serial_in => serial_in,
data_out => data_out
read_buffer => read_buffer
reset_buffer => reset_buffer,
en_16_x_baud => en_16_x_baud,
buffer_data_present => buffer_data_present,
buffer_full => buffer_full,
buffer_half_full => buffer_half_full,
clk => clk );
----------------------------------------------------------------------------------------
Providing Parity
----------------
Parity is defined as being ODD or EVEN. The term ODD and EVEN refers to the total number of
High (1) bits being transmitted including the parity bit itself.
For example the ASCII code for the letter 'A' is 41 hex. The 8-bit binary representation is
therefore 01000001 which clearly has an even number of 1's. So the parity bit will High (1)
for ODD parity and '0' for EVEN parity.
To transmit parity using the uart9_tx macro, the parity bit needs to be computed and then
applied along with the 8 data bits when activating the write_buffer control. This could be
achieved in hardware by creating an XOR gate for EVEN parity or an XNOR for ODD parity.
--ODD parity
data_in(8) <= data_in(0) xor data_in(1) xor data_in(2) xor data_in(3)
xor data_in(4) xor data_in(5) xor data_in(6) xor data_in(7);
PicoBlaze can also be used to calculate parity and may offer additional flexibility.
Since the ports and operation of PicoBlaze is 8-bits, connections to the uart_tx now
requires 2 ports. The first port can be used to provide the parity bit which will then
be held in a register. Then when the second port writes the main 8-bit data directly
into the FIFO buffer the parity bit is combined to form the complete 9-bit value. By
careful design the spare bits of the port used to set the parity bits can also be used
for control the reset on the UART FIFO buffers if required.
When receiving data, hardware logic could again be used to compute the parity of the data
and compare this with the received parity bit (XNOR gate). This would result in a
'parity error' flag which the associated processor would still need to read. So unless
the processor is really very occupied, it is probably easier and more efficient to read
the parity bit directly and perform the error test in software.
----------------------------------------------------------------------------------------
PicoBlaze interface to uart9_tx and uart_rx supporting parity.
The following sections of code describe a potential interface between PicoBlaze and the
uart9 macros. Notice how the FIFO buffers are fully controlled and monitored by the
Processor and the parity bit is treated as bit7 of allocated input and output ports.
----------------------------------------------------------------------------------------
signal rx_data : std_logic_vector(8 downto 0);
signal tx_data : std_logic_vector(8 downto 0);
signal tx_parity : std_logic;
signal write_to_uart : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal read_from_uart : std_logic;
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
signal uart_status : std_logic_vector(7 downto 0);
signal tx_reset : std_logic;
signal rx_reset : std_logic;
...............
--UART Transmitter interface
parity_tx_port: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- PORT 20 : UART FIFO control and transmitter parity.
if port_id(5)='1' then
tx_reset <= out_port(0);
rx_reset <= out_port(1);
tx_parity <= out_port(7);
end if;
end if;
end if;
end process parity_tx_port;
-- PORT 10 : Write data to UART transmitter.
write_to_uart <= write_strobe and port_id(4);
tx_data <= tx_parity & out_port;
transmit: uart9_tx
port map ( data_in => tx_data,
write_buffer => write_to_uart,
reset_buffer => reset_buffer,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
buffer_full => buffer_full,
buffer_half_full => buffer_half_full,
clk => clk );
...............
--UART Receiver interface
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(1 downto 0) is
--PORT 00 : Read FIFO status including receiver parity bit
when "00" => in_port <= uart_status;
--PORT 01 : Read receiver UART
when "01" => in_port <= rx_data(7 downto 0);
--PORT 02 - if required
--when "10" => in_port <= ?????;
--PORT 03 - if required
--when "11" => in_port <= ?????;
-- Don't care used to ensure minimum logic
when others => in_port <= "XXXXXXXX";
end case;
-- Form read strobe for UART receiver FIFO buffer for address 01.
read_from_uart <= read_strobe and (not port_id(1)) and port_id(0);
end if;
receive: uart9_rx
port map ( serial_in => rx,
data_out => rx_data,
read_buffer => read_from_uart,
reset_buffer => rx_reset,
en_16_x_baud => en_38400_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk );
uart_status <= rx_data(8) & "00" & rx_full & rx_half_full & rx_data_present & tx_full & tx_half_full ;
----------------------------------------------------------------------------------------
PicoBlaze to uart9_tx PSM code example
The following sections of PSM code relate to the VHDL interface above and enable a byte
of data to be transmitted or received via the UART including parity. CONSTANT directives
have been used to define both the port numbers and the allocations of bits within a given
port.
The parity generation is performed by the TEST instruction. It is vital that the
transmitter code (UART_write) sets the parity output port first and then writes the
actual data. The receiver code (UART_read) captures the received parity as part of the
polling of the FIFO status bits. It then reads the data, computes parity and compares this
with the received bit. The ZERO flag (Z) indicates any parity errors which can then be
used at the higher level in the program.
----------------------------------------------------------------------------------------
CONSTANT UART_write_port, 10 ;UART Tx 8-bit data output
;
CONSTANT UART_control_port, 20 ;UART reset and parity output
CONSTANT tx_reset, 01 ; Tx Buffer Reset - bit0
CONSTANT rx_reset, 02 ; Rx Buffer Reset - bit1
CONSTANT tx_parity, 80 ; Tx Parity - bit7
;
CONSTANT UART_status_port, 00 ;Communications status input
CONSTANT tx_half_full, 01 ; Transmitter half full - bit0
CONSTANT tx_full, 02 ; UART FIFO full - bit1
CONSTANT rx_data_present, 04 ; Receiver data present - bit2
CONSTANT rx_half_full, 08 ; UART FIFO half full - bit3
CONSTANT rx_full, 10 ; full - bit4
CONSTANT status_nul5, 20 ; unused - bit5
CONSTANT status_nul6, 40 ; unused - bit6
CONSTANT rx_parity, 80 ; Parity Bit parity - bit7
;
CONSTANT UART_read_port, 01 ;UART Rx 8-bit data input
;
NAMEREG sF, UART_data ;used for main 8-bit UART data
NAMEREG sE, UART_status ;used for UART status and control
;
;
;Write byte to UART with EVEN or ODD parity.
;
;Data should be provided in register 'UART_data'
;
;Odd and even Parity is describes the total number of 1's sent
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
;For EVEN parity comment out the line indicated ***.
;For ODD parity include the line indicated ***.
;
;Registers used s0, UART_data and UART_status
;
UART_write: INPUT UART_status, UART_status_port
TEST UART_status, tx_full ;test for space in buffer
JUMP NZ, UART_write ;wait if no space
LOAD s0, 00 ;compute parity for data being sent
TEST UART_data, FF
SRA s0 ;move parity value into MSB
XOR s0, 80 ;**** include this line for ODD parity
OUTPUT s0, UART_control_port ;send parity to UART (no reset)
OUTPUT UART_data, UART_write_port ;write data and parity into transmitter
RETURN
;
;Read byte from UART with test for EVEN or ODD parity.
;
;The routine tests and waits for available data and then reads the byte
;data into register 'UART_data'. The data is then tested against the parity
;bit received. For good data the ZERO flag will be set. A parity error will
;will be signified by the ZERO flag being reset.
;
;Odd and even Parity is describes the total number of 1's sent
;in the complete 9-bit packet formed of 8-bit data and the parity bit.
;For EVEN parity comment out the line indicated ***.
;For ODD parity include the line indicated ***.
;
;Registers used s0, UART_data and UART_status
;
;
UART_read: INPUT UART_status, UART_status_port ;Test for available character
TEST UART_status, rx_data_present ;test for space in buffer
INPUT UART_data, UART_read_port
LOAD s0, 00 ;compute parity for received data
TEST UART_data, FF
SRA s0
XOR s0, 80 ;****include this line for ODD parity
AND UART_status, rx_parity ;isolate parity bit received
XOR s0, UART_status ;ZERO set if parity matches
RETURN
;
----------------------------------------------------------------------------------------
Simple Error Correction Technique
---------------------------------
This is a very old technique which can provide a degree of error correction. Although a
parity error can indicate that an error has occurred, it is not possible to know which bit
has been received in error. This technique can be used to detect and correct the occasional
bit error.
In this example we assume that 8 bytes of data are to be sent. These are the ASCII characters
ABCDEFGH. First each byte is transmitted with ODD parity (although EVEN could also be used).
A 0 1 0 0 0 0 0 1 1
B 0 1 0 0 0 0 1 0 1
C 0 1 0 0 0 0 1 1 0
D 0 1 0 0 0 1 0 0 1
E 0 1 0 0 0 1 0 1 0
F 0 1 0 0 0 1 1 0 0
G 0 1 0 0 0 1 1 1 1
H 0 1 0 0 0 1 0 0 1
Next a 'parity byte' is transmitted. Each bit represents the ODD parity of the corresponding bit
transmitted in the last 8 bytes. In other words, it is the ODD parity associated with each of
the above columns.
1 1 1 1 1 0 1 1 *
It is debatable as to what to transmit as parity for this 'parity byte'. It could just be the
parity of the 'parity byte' in the normal way. It could be the parity of the previous 8 parity
bits transmitted or a combination of both. The uart9 macros allow you to make the choice in
software because it is treated the same way as any other data bit.
Now consider receiving the above data packet, but with a bit error at bit 6 of the character 'D'.
A 0 1 0 0 0 0 0 1 1
B 0 1 0 0 0 0 1 0 1
C 0 1 0 0 0 0 1 1 0
D 0 0 0 0 0 1 0 0 1 <----- Parity error
E 0 1 0 0 0 1 0 1 0
F 0 1 0 0 0 1 1 0 0
G 0 1 0 0 0 1 1 1 1
H 0 1 0 0 0 1 0 0 1
1 1 1 1 1 0 1 1 *
^
|
parity
error
The parity error on the 'D' line tells us there has been some kind of error but we do not know
which bit caused it. The 'parity byte' also indicates that an error has occurred in the bit 6
column, but we don't know which byte was the cause. However, it can easily be seen that the
intersection of these error points reveals the bit error and it would therefore be reasonable
to correct this bit by simple inversion.
It is possible to correct more than one bit error in a packet so long as the errors occur in
different rows and columns. There is always a danger that the parity bits may be corrupted and
this is where the parity of the 'parity byte' (*) could benefit from being the computation of
all 16 parity bits.
-----------------------------------------------------------------------------------------------
End of file UART9_readme.txt
-----------------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/bbfifo_16x8.vhd
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-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/bbfifo_16x9.vhd
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-- 'Bucket Brigade' FIFO
-- 16 deep
-- 9-bit data
--
-- Version : 1.00 (derived from bbfifo_16x8 version 1.10)
-- Version Date : 10th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x9
--
entity bbfifo_16x9 is
Port ( data_in : in std_logic_vector(8 downto 0);
data_out : out std_logic_vector(8 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x9;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x9
--
architecture low_level_definition of bbfifo_16x9 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x9
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x9 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 8 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x9.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/embedded_kcpsm3.vhd
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--
-- EMBEDDED_KCPSM3.VHD
--
-- Ken Chapman - Xilinx Ltd - 3rd June 2003
--
-- This file instantiates the KCPSM3 processor macro and connects the
-- program ROM.
--
-- NOTE: The name of the program ROM will probably need to be changed to
-- reflect the name of the program (PSM) file applied to the assembler.
--
------------------------------------------------------------------------------------
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity embedded_kcpsm3 is
Port ( port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
read_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end embedded_kcpsm3;
--
------------------------------------------------------------------------------------
--
-- Start of test achitecture
--
architecture connectivity of embedded_kcpsm3 is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component prog_rom
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
--
------------------------------------------------------------------------------------
--
-- Start of test circuit description
--
begin
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk);
program: prog_rom
port map( address => address,
instruction => instruction,
clk => clk);
end connectivity;
------------------------------------------------------------------------------------
--
-- END OF FILE EMBEDDED_KCPSM3.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/kcpsm3.vhd
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projects/PicoBlaze/ise/VHDL/kcpsm3_int_test.vhd
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--
-- Interrupt test for KCPSM3
--
-- Ken Chapman - Xilinx Ltd - June 2003
--
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity kcpsm3_int_test is
Port ( counter : out std_logic_vector(7 downto 0);
waveforms : out std_logic_vector(7 downto 0);
interrupt_event : in std_logic;
clk : in std_logic);
end kcpsm3_int_test;
--
------------------------------------------------------------------------------------
--
-- Start of test achitecture
--
architecture Behavioral of kcpsm3_int_test is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component int_test
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic :='0';
signal interrupt_ack : std_logic;
signal reset : std_logic;
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
-- Inserting KCPSM3 and the program memory
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk);
program: int_test
port map( address => address,
instruction => instruction,
clk => clk);
-- Unused inputs on processor
in_port <= "00000000";
reset <= '0';
-- Adding the output registers to the processor
IO_registers: process(clk)
begin
if clk'event and clk='1' then
-- waveform register at address 02
if port_id(1)='1' and write_strobe='1' then
waveforms <= out_port;
end if;
-- Interrupt Counter register at address 04
if port_id(2)='1' and write_strobe='1' then
counter <= out_port;
end if;
end if;
end process IO_registers;
-- Adding the interrupt input
-- Note that the initial value of interrupt (low) is
-- defined at signal declaration.
interrupt_control: process(clk)
begin
if clk'event and clk='1' then
if interrupt_ack='1' then
interrupt <= '0';
elsif interrupt_event='1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end process interrupt_control;
end Behavioral;
------------------------------------------------------------------------------------
--
-- END OF FILE KCPSM3_INT_TEST.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/kcuart9_rx.vhd
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-- 9-Bit Constant (K) Compact UART Receiver
--
-- 9 data bits, no parity, 1 stop bit
-- or
-- 8 data bits, parity, 1 stop bit
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
--
-- Version : 1.00 (derived from kcuart_rx version 1.00)
-- Version Date : 11th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART9_RX
--
entity kcuart9_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(8 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart9_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART9_RX
--
architecture low_level_definition of kcuart9_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART9_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(8 downto 0);
signal data_delay : std_logic_vector(8 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(9 downto 0);
signal valid_reg_delay : std_logic_vector(9 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART9_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 times baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 8 generate
begin
lsbs: if i<8 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=8 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(9),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 10x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 9 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay14_srl : label is "0000";
--
begin
delay14_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART9_RX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/kcuart9_tx.vhd
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-- Constant (K) Compact UART Transmitter
--
-- 9-Bit UART Transmitter
--
-- 9 data bits, no parity, 1 stop bit
-- or
-- 8 data bits, parity, 1 stop bit
-- where the value of the parity bit must be computed externally and provided as data_in(8).
--
-- NOTE : This macro is intended to be attached to bbfifo_16x9 and operation requires the
-- interaction of signals to and from that FIFO buffer to work correctly.
--
-- Version : 1.00 (derived from kcuart_tx version 1.10)
-- Version Date : 10th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART9_TX
--
entity kcuart9_tx is
Port ( data_in : in std_logic_vector(8 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
tx_complete : out std_logic;
clk : in std_logic);
end kcuart9_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART9_TX
--
architecture low_level_definition of kcuart9_tx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART9_TX
--
------------------------------------------------------------------------------------
--
signal data_01 : std_logic;
signal data_23 : std_logic;
signal data_45 : std_logic;
signal data_67 : std_logic;
signal data_0123 : std_logic;
signal data_4567 : std_logic;
signal data_01234567 : std_logic;
signal data_01234567_reg : std_logic;
signal data8_buf : std_logic;
signal force_serial : std_logic;
signal next_serial : std_logic;
signal bit_count : std_logic_vector(2 downto 0);
signal next_bit_count : std_logic_vector(2 downto 0);
signal half_bit_count : std_logic_vector(2 downto 0);
signal bit_count_cy : std_logic_vector(1 downto 0);
signal baud_count : std_logic_vector(3 downto 0);
signal next_baud_count : std_logic_vector(3 downto 0);
signal half_baud_count : std_logic_vector(3 downto 0);
signal baud_count_cy : std_logic_vector(3 downto 0);
signal tx_bit_en : std_logic;
signal decode7 : std_logic;
signal sel_last_bit : std_logic;
signal parity_bit : std_logic;
signal next_transmit : std_logic;
signal transmit : std_logic;
signal next_tx_complete : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of mux1_lut : label is "E4";
attribute INIT of mux2_lut : label is "E4";
attribute INIT of mux3_lut : label is "E4";
attribute INIT of mux4_lut : label is "E4";
attribute INIT of buf_data8 : label is "2";
attribute INIT of force_lut : label is "E0FF";
attribute INIT of count7_lut : label is "80";
attribute INIT of transmit_lut : label is "32";
attribute INIT of complete_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART9_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
mux1_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => bit_count(0),
I1 => data_in(0),
I2 => data_in(1),
O => data_01 );
mux2_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => bit_count(0),
I1 => data_in(2),
I2 => data_in(3),
O => data_23 );
mux3_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => bit_count(0),
I1 => data_in(4),
I2 => data_in(5),
O => data_45 );
mux4_lut: LUT3
--synthesis translate_off
generic map (INIT => X"E4")
--synthesis translate_on
port map( I0 => bit_count(0),
I1 => data_in(6),
I2 => data_in(7),
O => data_67 );
mux5_muxf5: MUXF5
port map( I1 => data_23,
I0 => data_01,
S => bit_count(1),
O => data_0123 );
mux6_muxf5: MUXF5
port map( I1 => data_67,
I0 => data_45,
S => bit_count(1),
O => data_4567 );
mux7_muxf6: MUXF6
port map( I1 => data_4567,
I0 => data_0123,
S => bit_count(2),
O => data_01234567 );
pipeline_mux: FD
port map ( D => data_01234567,
Q => data_01234567_reg,
C => clk);
-- Serial output logic
buf_data8: LUT1
--synthesis translate_off
generic map (INIT => X"2")
--synthesis translate_on
port map( I0 => data_in(8),
O => data8_buf );
force_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E0FF")
--synthesis translate_on
port map( I0 => data_01234567_reg,
I1 => parity_bit,
I2 => transmit,
I3 => send_character,
O => force_serial );
mux8_muxf5: MUXF5
port map( I1 => data8_buf,
I0 => force_serial,
S => sel_last_bit,
O => next_serial );
-- Final output flip-flop initialised to start at '1'
high_start: for i in 1 to 1 generate
--
attribute INIT : bit;
attribute INIT of output_reg : label is '1';
--
begin
output_reg: FDE
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
port map ( D => next_serial,
Q => serial_out,
CE => tx_bit_en,
C => clk);
end generate high_start;
-- bit counter
bit_count_loop: for i in 0 to 2 generate
--
attribute INIT : string;
attribute INIT of bit_count_lut : label is "B";
--
begin
bit_reg: FDE
port map ( D => next_bit_count(i),
Q => bit_count(i),
CE => tx_bit_en,
C => clk);
bit_count_lut: LUT2
--synthesis translate_off
generic map (INIT => X"B")
--synthesis translate_on
port map( I0 => bit_count(i),
I1 => transmit,
O => half_bit_count(i));
lsb_bit_count: if i=0 generate
begin
bit_count_xor: XORCY
port map( LI => half_bit_count(i),
CI => '1',
O => next_bit_count(i));
bit_count_muxcy: MUXCY
port map( DI => '0',
CI => '1',
S => half_bit_count(i),
O => bit_count_cy(i));
end generate lsb_bit_count;
upper_bit_count: if i>0 generate
begin
bit_count_xor: XORCY
port map( LI => half_bit_count(i),
CI => bit_count_cy(i-1),
O => next_bit_count(i));
middle_bit_count: if i=1 generate
begin
bit_count_muxcy: MUXCY
port map( DI => '0',
CI => bit_count_cy(i-1),
S => half_bit_count(i),
O => bit_count_cy(i));
end generate middle_bit_count;
end generate upper_bit_count;
end generate bit_count_loop;
-- baud counter
baud_count_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of baud_count_lut : label is "2";
--
begin
baud_reg: FDE
port map ( D => next_baud_count(i),
Q => baud_count(i),
CE => en_16_x_baud,
C => clk);
baud_count_lut: LUT1
--synthesis translate_off
generic map (INIT => X"2")
--synthesis translate_on
port map( I0 => baud_count(i),
O => half_baud_count(i));
lsb_baud_count: if i=0 generate
begin
baud_count_xor: XORCY
port map( LI => half_baud_count(i),
CI => en_16_x_baud,
O => next_baud_count(i));
baud_count_muxcy: MUXCY
port map( DI => '0',
CI => en_16_x_baud,
S => half_baud_count(i),
O => baud_count_cy(i));
end generate lsb_baud_count;
upper_baud_count: if i>0 generate
begin
baud_count_xor: XORCY
port map( LI => half_baud_count(i),
CI => baud_count_cy(i-1),
O => next_baud_count(i));
baud_count_muxcy: MUXCY
port map( DI => '0',
CI => baud_count_cy(i-1),
S => half_baud_count(i),
O => baud_count_cy(i));
end generate upper_baud_count;
end generate baud_count_loop;
bit_en_reg: FD
port map ( D => baud_count_cy(3),
Q => tx_bit_en,
C => clk);
-- state machine
count7_lut: LUT3
--synthesis translate_off
generic map (INIT => X"80")
--synthesis translate_on
port map( I0 => bit_count(0),
I1 => bit_count(1),
I2 => bit_count(2),
O => decode7 );
sel_last_reg: FDE
port map ( D => decode7,
Q => sel_last_bit,
CE => tx_bit_en,
C => clk);
parity_reg: FDE
port map ( D => sel_last_bit,
Q => parity_bit,
CE => tx_bit_en,
C => clk);
transmit_lut: LUT3
--synthesis translate_off
generic map (INIT => X"32")
--synthesis translate_on
port map( I0 => send_character,
I1 => parity_bit,
I2 => transmit,
O => next_transmit );
transmit_reg: FDE
port map ( D => next_transmit,
Q => transmit,
CE => tx_bit_en,
C => clk);
complete_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => parity_bit,
I1 => tx_bit_en,
O => next_tx_complete );
complete_reg: FD
port map ( D => next_tx_complete,
Q => tx_complete,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART9_TX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/kcuart_rx.vhd
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-- Constant (K) Compact UART Receiver
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_RX
--
entity kcuart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end kcuart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_RX
--
architecture low_level_definition of kcuart_rx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_RX
--
------------------------------------------------------------------------------------
--
signal sync_serial : std_logic;
signal stop_bit : std_logic;
signal data_int : std_logic_vector(7 downto 0);
signal data_delay : std_logic_vector(7 downto 0);
signal start_delay : std_logic;
signal start_bit : std_logic;
signal edge_delay : std_logic;
signal start_edge : std_logic;
signal decode_valid_char : std_logic;
signal valid_char : std_logic;
signal decode_purge : std_logic;
signal purge : std_logic;
signal valid_srl_delay : std_logic_vector(8 downto 0);
signal valid_reg_delay : std_logic_vector(8 downto 0);
signal decode_data_strobe : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of start_srl : label is "0000";
attribute INIT of edge_srl : label is "0000";
attribute INIT of valid_lut : label is "0040";
attribute INIT of purge_lut : label is "54";
attribute INIT of strobe_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Synchronise input serial data to system clock
sync_reg: FD
port map ( D => serial_in,
Q => sync_serial,
C => clk);
stop_reg: FD
port map ( D => sync_serial,
Q => stop_bit,
C => clk);
-- Data delays to capture data at 16 time baud rate
-- Each SRL16E is followed by a flip-flop for best timing
data_loop: for i in 0 to 7 generate
begin
lsbs: if i<7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(i+1),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate lsbs;
msb: if i=7 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => stop_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => data_delay(i) );
end generate msb;
data_reg: FDE
port map ( D => data_delay(i),
Q => data_int(i),
CE => en_16_x_baud,
C => clk);
end generate data_loop;
-- Assign internal signals to outputs
data_out <= data_int;
-- Data delays to capture start bit at 16 time baud rate
start_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_int(0),
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => start_delay );
start_reg: FDE
port map ( D => start_delay,
Q => start_bit,
CE => en_16_x_baud,
C => clk);
-- Data delays to capture start bit leading edge at 16 time baud rate
-- Delay ensures data is captured at mid-bit position
edge_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => start_bit,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '0',
Q => edge_delay );
edge_reg: FDE
port map ( D => edge_delay,
Q => start_edge,
CE => en_16_x_baud,
C => clk);
-- Detect a valid character
valid_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0040")
--synthesis translate_on
port map( I0 => purge,
I1 => stop_bit,
I2 => start_edge,
I3 => edge_delay,
O => decode_valid_char );
valid_reg: FDE
port map ( D => decode_valid_char,
Q => valid_char,
CE => en_16_x_baud,
C => clk);
-- Purge of data status
purge_lut: LUT3
--synthesis translate_off
generic map (INIT => X"54")
--synthesis translate_on
port map( I0 => valid_reg_delay(8),
I1 => valid_char,
I2 => purge,
O => decode_purge );
purge_reg: FDE
port map ( D => decode_purge,
Q => purge,
CE => en_16_x_baud,
C => clk);
-- Delay of valid_char pulse of length equivalent to the time taken
-- to purge data shift register of all data which has been used.
-- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with
-- up to 16 delays and utilising the dedicated flip flop in each stage.
valid_loop: for i in 0 to 8 generate
begin
lsb: if i=0 generate
--
attribute INIT : string;
attribute INIT of delay15_srl : label is "0000";
--
begin
delay15_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_char,
CE => en_16_x_baud,
CLK => clk,
A0 => '0',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate lsb;
msbs: if i>0 generate
--
attribute INIT : string;
attribute INIT of delay16_srl : label is "0000";
--
begin
delay16_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => valid_reg_delay(i-1),
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => valid_srl_delay(i) );
end generate msbs;
data_reg: FDE
port map ( D => valid_srl_delay(i),
Q => valid_reg_delay(i),
CE => en_16_x_baud,
C => clk);
end generate valid_loop;
-- Form data strobe
strobe_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => valid_char,
I1 => en_16_x_baud,
O => decode_data_strobe );
strobe_reg: FD
port map ( D => decode_data_strobe,
Q => data_strobe,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_RX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/kcuart_tx.vhd
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-- Constant (K) Compact UART Transmitter
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 2nd October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCUART_TX
--
entity kcuart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end kcuart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCUART_TX
--
architecture low_level_definition of kcuart_tx is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in KCUART_TX
--
------------------------------------------------------------------------------------
--
signal data_01 : std_logic;
signal data_23 : std_logic;
signal data_45 : std_logic;
signal data_67 : std_logic;
signal data_0123 : std_logic;
signal data_4567 : std_logic;
signal data_01234567 : std_logic;
signal bit_select : std_logic_vector(2 downto 0);
signal next_count : std_logic_vector(2 downto 0);
signal mask_count : std_logic_vector(2 downto 0);
signal mask_count_carry : std_logic_vector(2 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal ready_to_start : std_logic;
signal decode_Tx_start : std_logic;
signal Tx_start : std_logic;
signal decode_Tx_run : std_logic;
signal Tx_run : std_logic;
signal decode_hot_state : std_logic;
signal hot_state : std_logic;
signal hot_delay : std_logic;
signal Tx_bit : std_logic;
signal decode_Tx_stop : std_logic;
signal Tx_stop : std_logic;
signal decode_Tx_complete : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of mux1_lut : label is "E4FF";
attribute INIT of mux2_lut : label is "E4FF";
attribute INIT of mux3_lut : label is "E4FF";
attribute INIT of mux4_lut : label is "E4FF";
attribute INIT of ready_lut : label is "10";
attribute INIT of start_lut : label is "0190";
attribute INIT of run_lut : label is "1540";
attribute INIT of hot_state_lut : label is "94";
attribute INIT of delay14_srl : label is "0000";
attribute INIT of stop_lut : label is "0180";
attribute INIT of complete_lut : label is "8";
--
------------------------------------------------------------------------------------
--
-- Start of KCUART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
mux1_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(0),
I2 => data_in(1),
I3 => Tx_run,
O => data_01 );
mux2_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(2),
I2 => data_in(3),
I3 => Tx_run,
O => data_23 );
mux3_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(4),
I2 => data_in(5),
I3 => Tx_run,
O => data_45 );
mux4_lut: LUT4
--synthesis translate_off
generic map (INIT => X"E4FF")
--synthesis translate_on
port map( I0 => bit_select(0),
I1 => data_in(6),
I2 => data_in(7),
I3 => Tx_run,
O => data_67 );
mux5_muxf5: MUXF5
port map( I1 => data_23,
I0 => data_01,
S => bit_select(1),
O => data_0123 );
mux6_muxf5: MUXF5
port map( I1 => data_67,
I0 => data_45,
S => bit_select(1),
O => data_4567 );
mux7_muxf6: MUXF6
port map( I1 => data_4567,
I0 => data_0123,
S => bit_select(2),
O => data_01234567 );
-- Register serial output and force start and stop bits
pipeline_serial: FDRS
port map ( D => data_01234567,
Q => serial_out,
R => Tx_start,
S => Tx_stop,
C => clk);
-- 3-bit counter
-- Counter is clock enabled by en_16_x_baud
-- Counter will be reset when 'Tx_start' is active
-- Counter will increment when Tx_bit is active
-- Tx_run must be active to count
-- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow)
count_width_loop: for i in 0 to 2 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "8";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => bit_select(i),
CE => en_16_x_baud,
R => Tx_start,
C => clk);
count_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => bit_select(i),
I1 => Tx_run,
O => mask_count(i));
mask_and: MULT_AND
port map( I0 => bit_select(i),
I1 => Tx_run,
LO => mask_count_carry(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => Tx_bit,
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => Tx_bit,
O => next_count(i));
end generate lsb_count;
upper_count: if i>0 generate
begin
count_muxcy: MUXCY
port map( DI => mask_count_carry(i),
CI => count_carry(i-1),
S => mask_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => mask_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Ready to start decode
ready_lut: LUT3
--synthesis translate_off
generic map (INIT => X"10")
--synthesis translate_on
port map( I0 => Tx_run,
I1 => Tx_start,
I2 => send_character,
O => ready_to_start );
-- Start bit enable
start_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0190")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_stop,
I2 => ready_to_start,
I3 => Tx_start,
O => decode_Tx_start );
Tx_start_reg: FDE
port map ( D => decode_Tx_start,
Q => Tx_start,
CE => en_16_x_baud,
C => clk);
-- Run bit enable
run_lut: LUT4
--synthesis translate_off
generic map (INIT => X"1540")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => Tx_bit,
I2 => Tx_start,
I3 => Tx_run,
O => decode_Tx_run );
Tx_run_reg: FDE
port map ( D => decode_Tx_run,
Q => Tx_run,
CE => en_16_x_baud,
C => clk);
-- Bit rate enable
hot_state_lut: LUT3
--synthesis translate_off
generic map (INIT => X"94")
--synthesis translate_on
port map( I0 => Tx_stop,
I1 => ready_to_start,
I2 => Tx_bit,
O => decode_hot_state );
hot_state_reg: FDE
port map ( D => decode_hot_state,
Q => hot_state,
CE => en_16_x_baud,
C => clk);
delay14_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => hot_state,
CE => en_16_x_baud,
CLK => clk,
A0 => '1',
A1 => '0',
A2 => '1',
A3 => '1',
Q => hot_delay );
Tx_bit_reg: FDE
port map ( D => hot_delay,
Q => Tx_bit,
CE => en_16_x_baud,
C => clk);
-- Stop bit enable
stop_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0180")
--synthesis translate_on
port map( I0 => Tx_bit,
I1 => Tx_run,
I2 => count_carry(2),
I3 => Tx_stop,
O => decode_Tx_stop );
Tx_stop_reg: FDE
port map ( D => decode_Tx_stop,
Q => Tx_stop,
CE => en_16_x_baud,
C => clk);
-- Tx_complete strobe
complete_lut: LUT2
--synthesis translate_off
generic map (INIT => X"8")
--synthesis translate_on
port map( I0 => count_carry(2),
I1 => en_16_x_baud,
O => decode_Tx_complete );
Tx_complete_reg: FD
port map ( D => decode_Tx_complete,
Q => Tx_complete,
C => clk);
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE KCUART_TX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/test_bench.vhd
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-- Test Bench for kcpsm3_int_test.vhd
--
-- Ken Chapman - Xilinx Ltd - June 2003
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-- Design to be tested
COMPONENT kcpsm3_int_test
Port ( counter : out std_logic_vector(7 downto 0);
waveforms : out std_logic_vector(7 downto 0);
interrupt_event : in std_logic;
clk : in std_logic);
END COMPONENT;
-- signals to connect kcpsm3_int_test
SIGNAL counter : std_logic_vector(7 downto 0);
SIGNAL waveforms : std_logic_vector(7 downto 0);
SIGNAL interrupt_event : std_logic := '0';
SIGNAL clk : std_logic := '0';
BEGIN
-- Define the unit under test
uut: kcpsm3_int_test
port map ( counter => counter,
waveforms => waveforms,
interrupt_event => interrupt_event,
clk => clk);
-- Test Bench begins
-- Nominal 50MHz clock which also defines number of cycles in simulation
test_clock: process
variable max_cycles : integer :=400;
variable cycle_count : integer := 0;
begin
-- Define the clock cycles and the clock cycle counter
while cycle_count < max_cycles loop
clk <= '0';
wait for 10 ns;
clk <= '1';
cycle_count := cycle_count + 1;
wait for 10 ns;
--Now define stimulus relative to a given clock cycle
case cycle_count is
when 30 => interrupt_event <= '1';
when 67 => interrupt_event <= '1';
when 183 => interrupt_event <= '1';
when others => interrupt_event <= '0'; -- no interrupt
end case;
end loop;
wait; -- end of simulation.
end process;
END;
projects/PicoBlaze/ise/VHDL/uart9_rx.vhd
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-- 9-Bit UART Receiver with integral 16 byte FIFO buffer
--
-- 9 data bits, no parity, 1 stop bit
-- or
-- 8 data bits, parity, 1 stop bit
-- where the value of the parity bit must be checked externally and is provided as data_out(8).
--
-- Version : 1.00 (derived from uart_rx version 1.00)
-- Version Date : 11th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART9_RX
--
entity uart9_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(8 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart9_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART9_RX
--
architecture macro_level_definition of uart9_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART9_RX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Receiver
--
component kcuart9_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(8 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x9
Port ( data_in : in std_logic_vector(8 downto 0);
data_out : out std_logic_vector(8 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART9_RX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : std_logic_vector(8 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART9_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Constant (K) Compact UART 9-bit Receiver
receiver: kcuart9_rx
port map ( serial_in => serial_in,
data_out => uart_data_out,
data_strobe => fifo_write,
en_16_x_baud => en_16_x_baud,
clk => clk );
-- 9-bit 'Bucket Brigade' FIFO
buf: bbfifo_16x9
port map ( data_in => uart_data_out,
data_out => data_out,
reset => reset_buffer,
write => fifo_write,
read => read_buffer,
full => buffer_full,
half_full => buffer_half_full,
data_present => buffer_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART9_RX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/uart9_tx.vhd
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-- 9-Bit UART Transmitter with integral 16 byte FIFO buffer
--
-- 9 data bits, no parity, 1 stop bit
-- or
-- 8 data bits, parity, 1 stop bit
-- where the value of the parity bit must be computed externally and provided as data_in(8).
--
-- Version : 1.00 (derived from uart_tx version 1.00)
-- Version Date : 10th February 2005
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2005. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART9_TX
--
entity uart9_tx is
Port ( data_in : in std_logic_vector(8 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart9_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture macro_level_definition of uart9_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART9_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART 9-bit Transmitter
--
component kcuart9_tx
Port ( data_in : in std_logic_vector(8 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 9-bit 'Bucket Brigade' FIFO
--
component bbfifo_16x9
Port ( data_in : in std_logic_vector(8 downto 0);
data_out : out std_logic_vector(8 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART9_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(8 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- Constant (K) Compact UART 9-bit Transmitter
transmitter: kcuart9_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
-- 9-bit 'Bucket Brigade' FIFO
buf: bbfifo_16x9
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/uart_clock.vhd
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--
-- KCPSM3 reference design - Real Time Clock with UART communications
--
-- Ken Chapman - Xilinx Ltd - October 2003
--
-- The design demonstrates the following:-
-- Connection of KCPSM3 to Program ROM
-- Connection of UART macros supplied with PicoBlaze with
-- Baud rate generation
-- Definition of input and output ports with
-- Minimum decoding
-- Pipelining where appropriate
-- Interrupt circuit with
-- Simple fixed period timer
-- Automatic clearing using interrupt acknowledge from KCPSM3
--
-- The design is set up for a 55MHz system clock and UART communications rate of 38400 baud.
-- Please read design documentation to modify to your own requirements.
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2003. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Furthermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity uart_clock is
Port ( tx : out std_logic;
rx : in std_logic;
alarm : out std_logic;
clk : in std_logic);
end uart_clock;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of uart_clock is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM3
--
component kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- declaration of program ROM
--
component uclock
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
--
-- declaration of UART transmitter with integral 16 byte FIFO buffer
--
component uart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
-- declaration of UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM3 to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
--
-- Signals for connection of peripherals
--
signal uart_status_port : std_logic_vector(7 downto 0);
--
-- Signals to form an timer generating an interrupt every microsecond
--
signal timer_count : integer range 0 to 63 :=0;
signal timer_pulse : std_logic;
--
-- Signals for UART connections
--
signal baud_count : integer range 0 to 255 :=0;
signal en_16_x_baud : std_logic;
signal write_to_uart : std_logic;
signal tx_full : std_logic;
signal tx_half_full : std_logic;
signal read_from_uart : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_data_present : std_logic;
signal rx_full : std_logic;
signal rx_half_full : std_logic;
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 and the program memory
----------------------------------------------------------------------------------------------------------------------------------
--
processor: kcpsm3
port map( address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => '0',
clk => clk);
program_rom: uclock
port map( address => address,
instruction => instruction,
clk => clk);
--
----------------------------------------------------------------------------------------------------------------------------------
-- Interrupt
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- Interrupt is a generated once every 55 clock cycles to provide a 1us reference.
-- Interrupt is automatically cleared by interrupt acknowledgment from KCPSM3.
--
Timer: process(clk)
begin
if clk'event and clk='1' then
if timer_count=54 then
timer_count <= 0;
timer_pulse <= '1';
else
timer_count <= timer_count + 1;
timer_pulse <= '0';
end if;
if interrupt_ack = '1' then
interrupt <= '0';
elsif timer_pulse = '1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end process Timer;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 input ports
----------------------------------------------------------------------------------------------------------------------------------
--
--
-- UART FIFO status signals to form a bus
--
uart_status_port <= "000" & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full ;
--
-- The inputs connect via a pipelined multiplexer
--
input_ports: process(clk)
begin
if clk'event and clk='1' then
case port_id(0) is
-- read UART status at address 00 hex
when '0' => in_port <= uart_status_port;
-- read UART receive data at address 01 hex
when '1' => in_port <= rx_data;
-- Don't care used for all other addresses to ensure minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Form read strobe for UART receiver FIFO buffer.
-- The fact that the read strobe will occur after the actual data is read by
-- the KCPSM3 is acceptable because it is really means 'I have read you'!
read_from_uart <= read_strobe and port_id(0);
end if;
end process input_ports;
--
----------------------------------------------------------------------------------------------------------------------------------
-- KCPSM3 output ports
----------------------------------------------------------------------------------------------------------------------------------
--
-- adding the output registers to the clock processor
output_ports: process(clk)
begin
if clk'event and clk='1' then
if write_strobe='1' then
-- Alarm register at address 00 hex with data bit0 providing control
if port_id(0)='0' then
alarm <= out_port(0);
end if;
end if;
end if;
end process output_ports;
--
-- write to UART transmitter FIFO buffer at address 01 hex.
-- This is a combinatorial decode because the FIFO is the 'port register'.
--
write_to_uart <= write_strobe and port_id(0);
--
----------------------------------------------------------------------------------------------------------------------------------
-- UART
----------------------------------------------------------------------------------------------------------------------------------
--
-- Connect the 8-bit, 1 stop-bit, no parity transmit and receive macros.
-- Each contains an embedded 16-byte FIFO buffer.
--
transmit: uart_tx
port map ( data_in => out_port,
write_buffer => write_to_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
serial_out => tx,
buffer_full => tx_full,
buffer_half_full => tx_half_full,
clk => clk );
receive: uart_rx
port map ( serial_in => rx,
data_out => rx_data,
read_buffer => read_from_uart,
reset_buffer => '0',
en_16_x_baud => en_16_x_baud,
buffer_data_present => rx_data_present,
buffer_full => rx_full,
buffer_half_full => rx_half_full,
clk => clk );
--
-- Set baud rate to 38400 for the UART communications
-- Requires en_16_x_baud to be 614400Hz which is a single cycle pulse every 163 cycles at 100MHz
--
-- NOTE : If the highest value for baud_count exceeds 127 you will need to adjust
-- the range of integers in the signal declaration for baud_count.
--
baud_timer: process(clk)
begin
if clk'event and clk='1' then
if baud_count=162 then
baud_count <= 0;
en_16_x_baud <= '1';
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_timer;
----------------------------------------------------------------------------------------------------------------------------------
end Behavioral;
------------------------------------------------------------------------------------------------------------------------------------
--
-- END OF FILE uart_clock.vhd
--
------------------------------------------------------------------------------------------------------------------------------------
projects/PicoBlaze/ise/VHDL/uart_rx.vhd
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-- UART Receiver with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 16th October 2002
--
-- Start of design entry : 16th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_RX
--
entity uart_rx is
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
read_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
buffer_data_present : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_rx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_RX
--
architecture macro_level_definition of uart_rx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_RX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Receiver
--
component kcuart_rx
Port ( serial_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strobe : out std_logic;
en_16_x_baud : in std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_RX
--
------------------------------------------------------------------------------------
--
signal uart_data_out : std_logic_vector(7 downto 0);
signal fifo_write : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_RX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_rx
port map ( serial_in => serial_in,
data_out => uart_data_out,
data_strobe => fifo_write,
en_16_x_baud => en_16_x_baud,
clk => clk );
buf: bbfifo_16x8
port map ( data_in => uart_data_out,
data_out => data_out,
reset => reset_buffer,
write => fifo_write,
read => read_buffer,
full => buffer_full,
half_full => buffer_half_full,
data_present => buffer_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_RX.VHD
--
------------------------------------------------------------------------------------
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-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for UART_TX
--
entity uart_tx is
Port ( data_in : in std_logic_vector(7 downto 0);
write_buffer : in std_logic;
reset_buffer : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_full : out std_logic;
buffer_half_full : out std_logic;
clk : in std_logic);
end uart_tx;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for UART_TX
--
architecture macro_level_definition of uart_tx is
--
------------------------------------------------------------------------------------
--
-- Components used in UART_TX and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- Constant (K) Compact UART Transmitter
--
component kcuart_tx
Port ( data_in : in std_logic_vector(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic);
end component;
--
-- 'Bucket Brigade' FIFO
--
component bbfifo_16x8
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in UART_TX
--
------------------------------------------------------------------------------------
--
signal fifo_data_out : std_logic_vector(7 downto 0);
signal fifo_data_present : std_logic;
signal fifo_read : std_logic;
--
------------------------------------------------------------------------------------
--
-- Start of UART_TX circuit description
--
------------------------------------------------------------------------------------
--
begin
-- 8 to 1 multiplexer to convert parallel data to serial
kcuart: kcuart_tx
port map ( data_in => fifo_data_out,
send_character => fifo_data_present,
en_16_x_baud => en_16_x_baud,
serial_out => serial_out,
Tx_complete => fifo_read,
clk => clk);
buf: bbfifo_16x8
port map ( data_in => data_in,
data_out => fifo_data_out,
reset => reset_buffer,
write => write_buffer,
read => fifo_read,
full => buffer_full,
half_full => buffer_half_full,
data_present => fifo_data_present,
clk => clk);
end macro_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE UART_TX.VHD
--
------------------------------------------------------------------------------------