- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1416 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
@@ -0,0 +1,111 @@
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Table of constant values and their specified constant labels.
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00 UART_status_port
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01 tx_half_full
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02 tx_full
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04 rx_half_full
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08 rx_full
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10 rx_data_present
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01 UART_read_port
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01 UART_write_port
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00 alarm_port
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01 alarm_control
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00 us_time_stamp_lsb
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01 us_time_stamp_msb
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02 us_time_lsb
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03 us_time_msb
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04 ms_time_lsb
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05 ms_time_msb
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06 real_time_hours
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07 real_time_minutes
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08 real_time_seconds
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09 alarm_time_hours
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0A alarm_time_minutes
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0B alarm_time_seconds
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0C alarm_status
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01 alarm_active
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02 alarm_armed
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10 time_preserve0
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11 time_preserve1
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12 time_preserve2
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13 time_preserve3
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14 time_preserve4
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15 time_preserve5
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20 string_start
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E8 count_1000_lsb
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03 count_1000_msb
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18 hours_in_a_day
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3C minutes_in_an_hour
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3C seconds_in_a_minute
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61 character_a
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62 character_b
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63 character_c
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64 character_d
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65 character_e
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66 character_f
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67 character_g
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68 character_h
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69 character_i
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6A character_j
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6B character_k
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6C character_l
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6D character_m
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6E character_n
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6F character_o
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70 character_p
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71 character_q
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72 character_r
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73 character_s
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74 character_t
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75 character_u
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76 character_v
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77 character_w
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78 character_x
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79 character_y
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7A character_z
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41 character_A
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42 character_B
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43 character_C
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44 character_D
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45 character_E
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46 character_F
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47 character_G
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48 character_H
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49 character_I
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4A character_J
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4B character_K
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4C character_L
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4D character_M
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4E character_N
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4F character_O
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50 character_P
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51 character_Q
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52 character_R
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53 character_S
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54 character_T
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55 character_U
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56 character_V
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57 character_W
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58 character_X
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59 character_Y
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5A character_Z
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30 character_0
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31 character_1
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32 character_2
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33 character_3
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34 character_4
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35 character_5
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36 character_6
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37 character_7
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38 character_8
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39 character_9
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3A character_colon
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3B character_semi_colon
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3C character_less_than
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3E character_greater_than
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3D character_equals
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20 character_space
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0D character_CR
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3F character_question
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24 character_dollar
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08 character_BS
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@@ -0,0 +1,92 @@
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component_name=int_test;
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width_a=18;
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depth_a=1024;
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configuration_port_a=read_only;
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port_a_enable_pin=false;
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port_a_handshaking_pins=false;
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port_a_register_inputs=false;
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port_a_init_pin=false;
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port_a_init_value=00000;
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port_a_additional_output_pipe_stages = 0;
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port_a_register_inputs = false;
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port_a_active_clock_edge = Rising_Edge_Triggered;
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width_b=18;
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depth_b=1024;
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configuration_port_b=read_and_write;
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write_mode_port_b=read_after_write;
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port_b_enable_pin=false;
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port_b_handshaking_pins=false;
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port_b_register_inputs=false;
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port_b_init_pin=false;
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port_b_init_value=00000;
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port_b_additional_output_pipe_stages = 0;
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port_b_register_inputs = false;
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port_b_active_clock_edge = Rising_Edge_Triggered;
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port_b_write_enable_polarity = Active_High;
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memory_initialization_radix=16;
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global_init_value=00000;
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memory_initialization_vector=
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00A00, 002AA, 3C001, 2C202, 00007, 1C001, 35405, 0E2FF, 34003, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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18A01, 2CA04, 38001, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
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00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 342B0;
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,25 @@
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;Interrupt example
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;
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CONSTANT waveform_port, 02 ;bit0 will be data
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CONSTANT counter_port, 04
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CONSTANT pattern_10101010, AA
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NAMEREG sA, interrupt_counter
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;
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start: LOAD interrupt_counter, 00 ;reset interrupt counter
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LOAD s2, pattern_10101010 ;initial output condition
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ENABLE INTERRUPT
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;
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drive_wave: OUTPUT s2, waveform_port
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LOAD s0, 07 ;delay size
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loop: SUB s0, 01 ;delay loop
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JUMP NZ, loop
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XOR s2, FF ;toggle waveform
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JUMP drive_wave
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;
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ADDRESS 2B0
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int_routine: ADD interrupt_counter, 01 ;increment counter
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OUTPUT interrupt_counter, counter_port
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RETURNI ENABLE
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;
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ADDRESS 3FF ;set interrupt vector
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JUMP int_routine
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,32 @@
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KCPSM3 Assembler log file for program 'int_test.psm'.
|
||||
Generated by KCPSM3 version 1.30
|
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Ken Chapman (Xilinx Ltd) 2005.
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25Sep2005-14:54:47
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Addr Code
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000 ;Interrupt example
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000 ;
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000 CONSTANT waveform_port, 02 ;bit0 will be data
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000 CONSTANT counter_port, 04
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000 CONSTANT pattern_10101010, AA
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000 NAMEREG sA, interrupt_counter
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||||
000 ;
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||||
000 00A00 start: LOAD interrupt_counter[sA], 00 ;reset interrupt counter
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001 002AA LOAD s2, pattern_10101010[AA] ;initial output condition
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002 3C001 ENABLE INTERRUPT
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003 ;
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003 2C202 drive_wave: OUTPUT s2, waveform_port[02]
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004 00007 LOAD s0, 07 ;delay size
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005 1C001 loop: SUB s0, 01 ;delay loop
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006 35405 JUMP NZ, loop[005]
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007 0E2FF XOR s2, FF ;toggle waveform
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008 34003 JUMP drive_wave[003]
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009 ;
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2B0 ADDRESS 2B0
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2B0 18A01 int_routine: ADD interrupt_counter[sA], 01 ;increment counter
|
||||
2B1 2CA04 OUTPUT interrupt_counter[sA], counter_port[04]
|
||||
2B2 38001 RETURNI ENABLE
|
||||
2B3 ;
|
||||
3FF ADDRESS 3FF ;set interrupt vector
|
||||
3FF 342B0 JUMP int_routine[2B0]
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@@ -0,0 +1,69 @@
|
||||
function bits = fill_int_test_program_store()
|
||||
bits = [ ...
|
||||
2560, 682, 245761, 180738, 7, 114689, 218117, 58111, 212995, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
100865, 182788, 229377, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 213680, ...
|
||||
];
|
||||
|
||||
return;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,262 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: int_test.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 int_test.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: int_test
|
||||
//Generated 25Sep2005-14:54:47.
|
||||
//Purpose:
|
||||
// int_test verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ps / 1ps
|
||||
module int_test (address, instruction, clk);
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
output [17:0] instruction;
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00"
|
||||
init_01 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_02 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_03 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_05 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_07 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_08 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_09 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_0F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_10 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_11 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_12 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_13 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_14 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_15 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_16 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_17 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_18 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_19 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_1F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2B = "00000000000000000000000000000000000000000000000000008001CA048A01"
|
||||
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3F = "42B0000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_00 = "00000000000000000000000000000000000000000000000000000000000334B0"
|
||||
initp_01 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_02 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_03 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_05 = "0000000000000000000000000000000000000039000000000000000000000000"
|
||||
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_07 = "C000000000000000000000000000000000000000000000000000000000000000" */;
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00;
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h00000000000000000000000000000000000000000000000000008001CA048A01;
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h42B0000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_00 = 256'h00000000000000000000000000000000000000000000000000000000000334B0;
|
||||
defparam ram_1024_x_18.INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000039000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_07 = 256'hC000000000000000000000000000000000000000000000000000000000000000;
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "00000000000000000000000000000000000000000000000000008001CA048A01"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "42B0000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "00000000000000000000000000000000000000000000000000000000000334B0"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000039000000000000000000000000"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "C000000000000000000000000000000000000000000000000000000000000000"
|
||||
endmodule
|
||||
// END OF FILE int_test.v
|
||||
@@ -0,0 +1,274 @@
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by int_test.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler 25Sep2005-14:54:47.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity int_test is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end int_test;
|
||||
--
|
||||
architecture low_level_definition of int_test is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000000008001CA048A01";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "42B0000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "00000000000000000000000000000000000000000000000000000000000334B0";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000039000000000000000000000000";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "C000000000000000000000000000000000000000000000000000000000000000";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"00000000000000000000000000004003E2FF5405C0010007C202C00102AA0A00",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"00000000000000000000000000000000000000000000000000008001CA048A01",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"42B0000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_00 => X"00000000000000000000000000000000000000000000000000000000000334B0",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000039000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"C000000000000000000000000000000000000000000000000000000000000000")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE int_test.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
Binary file not shown.
@@ -0,0 +1,63 @@
|
||||
Table of addresses and their specified labels.
|
||||
|
||||
000 cold_start
|
||||
012 prompt_input
|
||||
01C bad_input_command
|
||||
01E test_for_TIME
|
||||
02C set_time_command
|
||||
037 test_for_ALARM
|
||||
048 set_alarm_command
|
||||
055 set_alarm_on_off
|
||||
060 test_OFF
|
||||
06D test_time_string
|
||||
08B invalid_time
|
||||
091 fetch_char_from_memory
|
||||
095 read_from_UART
|
||||
09A read_character
|
||||
09D send_to_UART
|
||||
0A2 UART_write
|
||||
0A4 alarm_drive
|
||||
0A8 transmit_time
|
||||
0AC transmit_alarm_time
|
||||
0B6 test_armed
|
||||
0BA alarm_is_off
|
||||
0BC transmit_string
|
||||
0BD next_char_tx
|
||||
0C3 receive_string
|
||||
0C6 receive_full_test
|
||||
0D3 BS_edit
|
||||
0D9 string_start_again
|
||||
0DB read_error
|
||||
0DF clear_UART_Rx_loop
|
||||
0E4 send_CR
|
||||
0E7 send_space
|
||||
0EA send_backspace
|
||||
0ED send_Syntax_Error
|
||||
0FA send_Overflow_Error
|
||||
10A send_space_Error
|
||||
10B send_Error
|
||||
115 send_prompt
|
||||
122 send_greater_than
|
||||
125 send_Invalid
|
||||
134 send_Time
|
||||
13D send_Alarm
|
||||
148 send_OFF
|
||||
14E send_ON
|
||||
153 send_Active
|
||||
160 time_to_ASCII
|
||||
17E decimal_to_ASCII
|
||||
17F test_for_ten
|
||||
185 update_time
|
||||
19A test_1000us
|
||||
19F store_us_time
|
||||
1AD restore_ms_time
|
||||
1AF store_ms_time
|
||||
1B7 inc_minutes
|
||||
1BF inc_hours
|
||||
1C7 reset_hours
|
||||
1C9 time_update_complete
|
||||
1DB finish_update
|
||||
1E2 upper_case
|
||||
1E8 1char_to_value
|
||||
1EC 2char_to_value
|
||||
3FC ISR
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,29 @@
|
||||
component_name={name};
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
|
||||
@@ -0,0 +1,350 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: 1.02
|
||||
// \ \ Filename: ROM_form.v
|
||||
// / / Date Last Modified: September 7 2004
|
||||
// /___/ /\ Date Created: July 2003
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Device: Xilinx
|
||||
//Purpose:
|
||||
// This is the Verilog template file for the KCPSM3 assembler.
|
||||
// It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block
|
||||
// RAM to act as a single port program ROM.
|
||||
//
|
||||
// This Verilog file is not valid as input directly into a synthesis or
|
||||
// simulation tool. The assembler will read this template and insert the
|
||||
// data required to complete the definition of program ROM and write it out
|
||||
// to a new '.v' file associated with the name of the original '.psm' file
|
||||
// being assembled.
|
||||
//
|
||||
// This template can be modified to define alternative memory definitions
|
||||
// such as dual port. However, you are responsible for ensuring the template
|
||||
// is correct as the assembler does not perform any checking of the Verilog.
|
||||
//
|
||||
// The assembler identifies all text enclosed by {} characters, and replaces
|
||||
// these character strings. All templates should include these {} character
|
||||
// strings for the assembler to work correctly.
|
||||
//
|
||||
// This template defines a block RAM configured in 1024 x 18-bit single port
|
||||
// mode and conneceted to act as a single port ROM.
|
||||
//
|
||||
//Reference:
|
||||
// None
|
||||
//Revision History:
|
||||
// Rev 1.00 - jc - Converted to verilog, July 2003.
|
||||
// Rev 1.01 - sus - Added text to confirm to Xilinx HDL std, August 4 2004.
|
||||
// Rev 1.02 - njs - Added attributes for Synplicity August 5 2004.
|
||||
// Rev 1.03 - sus - Added text to conform to Xilinx generated
|
||||
// HDL spec, September 7 2004
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Contact: e-mail picoblaze@xilinx.com
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Disclaimer:
|
||||
// LIMITED WARRANTY AND DISCLAIMER. These designs are
|
||||
// provided to you "as is". Xilinx and its licensors make and you
|
||||
// receive no warranties or conditions, express, implied,
|
||||
// statutory or otherwise, and Xilinx specifically disclaims any
|
||||
// implied warranties of merchantability, non-infringement, or
|
||||
// fitness for a particular purpose. Xilinx does not warrant that
|
||||
// the functions contained in these designs will meet your
|
||||
// requirements, or that the operation of these designs will be
|
||||
// uninterrupted or error free, or that defects in the Designs
|
||||
// will be corrected. Furthermore, Xilinx does not warrant or
|
||||
// make any representations regarding use or the results of the
|
||||
// use of the designs in terms of correctness, accuracy,
|
||||
// reliability, or otherwise.
|
||||
//
|
||||
// LIMITATION OF LIABILITY. In no event will Xilinx or its
|
||||
// licensors be liable for any loss of data, lost profits, cost
|
||||
// or procurement of substitute goods or services, or for any
|
||||
// special, incidental, consequential, or indirect damages
|
||||
// arising from the use or operation of the designs or
|
||||
// accompanying documentation, however caused and on any theory
|
||||
// of liability. This limitation will apply even if Xilinx
|
||||
// has been advised of the possibility of such damage. This
|
||||
// limitation shall apply not-withstanding the failure of the
|
||||
// essential purpose of any limited remedies herein.
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: {name}.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 {name}.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: {name}
|
||||
//Generated {timestamp}.
|
||||
//Purpose:
|
||||
// {name} verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`timescale 1 ps / 1ps
|
||||
|
||||
module {name} (address, instruction, clk);
|
||||
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
|
||||
output [17:0] instruction;
|
||||
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "{INIT_00}"
|
||||
init_01 = "{INIT_01}"
|
||||
init_02 = "{INIT_02}"
|
||||
init_03 = "{INIT_03}"
|
||||
init_04 = "{INIT_04}"
|
||||
init_05 = "{INIT_05}"
|
||||
init_06 = "{INIT_06}"
|
||||
init_07 = "{INIT_07}"
|
||||
init_08 = "{INIT_08}"
|
||||
init_09 = "{INIT_09}"
|
||||
init_0A = "{INIT_0A}"
|
||||
init_0B = "{INIT_0B}"
|
||||
init_0C = "{INIT_0C}"
|
||||
init_0D = "{INIT_0D}"
|
||||
init_0E = "{INIT_0E}"
|
||||
init_0F = "{INIT_0F}"
|
||||
init_10 = "{INIT_10}"
|
||||
init_11 = "{INIT_11}"
|
||||
init_12 = "{INIT_12}"
|
||||
init_13 = "{INIT_13}"
|
||||
init_14 = "{INIT_14}"
|
||||
init_15 = "{INIT_15}"
|
||||
init_16 = "{INIT_16}"
|
||||
init_17 = "{INIT_17}"
|
||||
init_18 = "{INIT_18}"
|
||||
init_19 = "{INIT_19}"
|
||||
init_1A = "{INIT_1A}"
|
||||
init_1B = "{INIT_1B}"
|
||||
init_1C = "{INIT_1C}"
|
||||
init_1D = "{INIT_1D}"
|
||||
init_1E = "{INIT_1E}"
|
||||
init_1F = "{INIT_1F}"
|
||||
init_20 = "{INIT_20}"
|
||||
init_21 = "{INIT_21}"
|
||||
init_22 = "{INIT_22}"
|
||||
init_23 = "{INIT_23}"
|
||||
init_24 = "{INIT_24}"
|
||||
init_25 = "{INIT_25}"
|
||||
init_26 = "{INIT_26}"
|
||||
init_27 = "{INIT_27}"
|
||||
init_28 = "{INIT_28}"
|
||||
init_29 = "{INIT_29}"
|
||||
init_2A = "{INIT_2A}"
|
||||
init_2B = "{INIT_2B}"
|
||||
init_2C = "{INIT_2C}"
|
||||
init_2D = "{INIT_2D}"
|
||||
init_2E = "{INIT_2E}"
|
||||
init_2F = "{INIT_2F}"
|
||||
init_30 = "{INIT_30}"
|
||||
init_31 = "{INIT_31}"
|
||||
init_32 = "{INIT_32}"
|
||||
init_33 = "{INIT_33}"
|
||||
init_34 = "{INIT_34}"
|
||||
init_35 = "{INIT_35}"
|
||||
init_36 = "{INIT_36}"
|
||||
init_37 = "{INIT_37}"
|
||||
init_38 = "{INIT_38}"
|
||||
init_39 = "{INIT_39}"
|
||||
init_3A = "{INIT_3A}"
|
||||
init_3B = "{INIT_3B}"
|
||||
init_3C = "{INIT_3C}"
|
||||
init_3D = "{INIT_3D}"
|
||||
init_3E = "{INIT_3E}"
|
||||
init_3F = "{INIT_3F}"
|
||||
initp_00 = "{INITP_00}"
|
||||
initp_01 = "{INITP_01}"
|
||||
initp_02 = "{INITP_02}"
|
||||
initp_03 = "{INITP_03}"
|
||||
initp_04 = "{INITP_04}"
|
||||
initp_05 = "{INITP_05}"
|
||||
initp_06 = "{INITP_06}"
|
||||
initp_07 = "{INITP_07}" */;
|
||||
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h{INIT_00};
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h{INIT_01};
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h{INIT_02};
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h{INIT_03};
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h{INIT_04};
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h{INIT_05};
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h{INIT_06};
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h{INIT_07};
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h{INIT_08};
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h{INIT_09};
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h{INIT_0A};
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h{INIT_0B};
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h{INIT_0C};
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h{INIT_0D};
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h{INIT_0E};
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h{INIT_0F};
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h{INIT_10};
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h{INIT_11};
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h{INIT_12};
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h{INIT_13};
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h{INIT_14};
|
||||
defparam ram_1024_x_18.INIT_15 = 256'h{INIT_15};
|
||||
defparam ram_1024_x_18.INIT_16 = 256'h{INIT_16};
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h{INIT_17};
|
||||
defparam ram_1024_x_18.INIT_18 = 256'h{INIT_18};
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h{INIT_19};
|
||||
defparam ram_1024_x_18.INIT_1A = 256'h{INIT_1A};
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h{INIT_1B};
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h{INIT_1C};
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h{INIT_1D};
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h{INIT_1E};
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h{INIT_1F};
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h{INIT_20};
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h{INIT_21};
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h{INIT_22};
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h{INIT_23};
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h{INIT_24};
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h{INIT_25};
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h{INIT_26};
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h{INIT_27};
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h{INIT_28};
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h{INIT_29};
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h{INIT_2A};
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h{INIT_2B};
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h{INIT_2C};
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h{INIT_2D};
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h{INIT_2E};
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h{INIT_2F};
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h{INIT_30};
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h{INIT_31};
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h{INIT_32};
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h{INIT_33};
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h{INIT_34};
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h{INIT_35};
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h{INIT_36};
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h{INIT_37};
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h{INIT_38};
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h{INIT_39};
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h{INIT_3A};
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h{INIT_3B};
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h{INIT_3C};
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h{INIT_3D};
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h{INIT_3E};
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h{INIT_3F};
|
||||
defparam ram_1024_x_18.INITP_00 = 256'h{INITP_00};
|
||||
defparam ram_1024_x_18.INITP_01 = 256'h{INITP_01};
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h{INITP_02};
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h{INITP_03};
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h{INITP_04};
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h{INITP_05};
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h{INITP_06};
|
||||
defparam ram_1024_x_18.INITP_07 = 256'h{INITP_07};
|
||||
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "{INIT_00}"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "{INIT_01}"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "{INIT_02}"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "{INIT_03}"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "{INIT_04}"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "{INIT_05}"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "{INIT_06}"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "{INIT_07}"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "{INIT_08}"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "{INIT_09}"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "{INIT_0A}"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "{INIT_0B}"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "{INIT_0C}"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "{INIT_0D}"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "{INIT_0E}"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "{INIT_0F}"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "{INIT_10}"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "{INIT_11}"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "{INIT_12}"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "{INIT_13}"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "{INIT_14}"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "{INIT_15}"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "{INIT_16}"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "{INIT_17}"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "{INIT_18}"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "{INIT_19}"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "{INIT_1A}"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "{INIT_1B}"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "{INIT_1C}"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "{INIT_1D}"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "{INIT_1E}"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "{INIT_1F}"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "{INIT_20}"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "{INIT_21}"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "{INIT_22}"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "{INIT_23}"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "{INIT_24}"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "{INIT_25}"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "{INIT_26}"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "{INIT_27}"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "{INIT_28}"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "{INIT_29}"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "{INIT_2A}"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "{INIT_2B}"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "{INIT_2C}"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "{INIT_2D}"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "{INIT_2E}"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "{INIT_2F}"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "{INIT_30}"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "{INIT_31}"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "{INIT_32}"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "{INIT_33}"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "{INIT_34}"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "{INIT_35}"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "{INIT_36}"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "{INIT_37}"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "{INIT_38}"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "{INIT_39}"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "{INIT_3A}"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "{INIT_3B}"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "{INIT_3C}"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "{INIT_3D}"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "{INIT_3E}"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "{INIT_3F}"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "{INITP_00}"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "{INITP_01}"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "{INITP_02}"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "{INITP_03}"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "{INITP_04}"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "{INITP_05}"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "{INITP_06}"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "{INITP_07}"
|
||||
|
||||
endmodule
|
||||
|
||||
// END OF FILE {name}.v
|
||||
@@ -0,0 +1,305 @@
|
||||
ROM_form.vhd
|
||||
|
||||
Ken Chapman (Xilinx Ltd) July 2003
|
||||
|
||||
This is the VHDL template file for the KCPSM3 assembler.
|
||||
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
|
||||
a single port program ROM.
|
||||
|
||||
This VHDL file is not valid as input directly into a synthesis or simulation tool.
|
||||
The assembler will read this template and insert the data required to complete the
|
||||
definition of program ROM and write it out to a new '.vhd' file associated with the
|
||||
name of the original '.psm' file being assembled.
|
||||
|
||||
This template can be modified to define alternative memory definitions such as dual port.
|
||||
However, you are responsible for ensuring the template is correct as the assembler does
|
||||
not perform any checking of the VHDL.
|
||||
|
||||
The assembler identifies all text enclosed by {} characters, and replaces these
|
||||
character strings. All templates should include these {} character strings for
|
||||
the assembler to work correctly.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
This template defines a block RAM configured in 1024 x 18-bit single port mode and
|
||||
conneceted to act as a single port ROM.
|
||||
|
||||
****************************************************************************************
|
||||
|
||||
The next line is used to determine where the template actually starts and must exist.
|
||||
{begin template}
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler {timestamp}.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity {name} is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end {name};
|
||||
--
|
||||
architecture low_level_definition of {name} is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"{INIT_00}",
|
||||
INIT_01 => X"{INIT_01}",
|
||||
INIT_02 => X"{INIT_02}",
|
||||
INIT_03 => X"{INIT_03}",
|
||||
INIT_04 => X"{INIT_04}",
|
||||
INIT_05 => X"{INIT_05}",
|
||||
INIT_06 => X"{INIT_06}",
|
||||
INIT_07 => X"{INIT_07}",
|
||||
INIT_08 => X"{INIT_08}",
|
||||
INIT_09 => X"{INIT_09}",
|
||||
INIT_0A => X"{INIT_0A}",
|
||||
INIT_0B => X"{INIT_0B}",
|
||||
INIT_0C => X"{INIT_0C}",
|
||||
INIT_0D => X"{INIT_0D}",
|
||||
INIT_0E => X"{INIT_0E}",
|
||||
INIT_0F => X"{INIT_0F}",
|
||||
INIT_10 => X"{INIT_10}",
|
||||
INIT_11 => X"{INIT_11}",
|
||||
INIT_12 => X"{INIT_12}",
|
||||
INIT_13 => X"{INIT_13}",
|
||||
INIT_14 => X"{INIT_14}",
|
||||
INIT_15 => X"{INIT_15}",
|
||||
INIT_16 => X"{INIT_16}",
|
||||
INIT_17 => X"{INIT_17}",
|
||||
INIT_18 => X"{INIT_18}",
|
||||
INIT_19 => X"{INIT_19}",
|
||||
INIT_1A => X"{INIT_1A}",
|
||||
INIT_1B => X"{INIT_1B}",
|
||||
INIT_1C => X"{INIT_1C}",
|
||||
INIT_1D => X"{INIT_1D}",
|
||||
INIT_1E => X"{INIT_1E}",
|
||||
INIT_1F => X"{INIT_1F}",
|
||||
INIT_20 => X"{INIT_20}",
|
||||
INIT_21 => X"{INIT_21}",
|
||||
INIT_22 => X"{INIT_22}",
|
||||
INIT_23 => X"{INIT_23}",
|
||||
INIT_24 => X"{INIT_24}",
|
||||
INIT_25 => X"{INIT_25}",
|
||||
INIT_26 => X"{INIT_26}",
|
||||
INIT_27 => X"{INIT_27}",
|
||||
INIT_28 => X"{INIT_28}",
|
||||
INIT_29 => X"{INIT_29}",
|
||||
INIT_2A => X"{INIT_2A}",
|
||||
INIT_2B => X"{INIT_2B}",
|
||||
INIT_2C => X"{INIT_2C}",
|
||||
INIT_2D => X"{INIT_2D}",
|
||||
INIT_2E => X"{INIT_2E}",
|
||||
INIT_2F => X"{INIT_2F}",
|
||||
INIT_30 => X"{INIT_30}",
|
||||
INIT_31 => X"{INIT_31}",
|
||||
INIT_32 => X"{INIT_32}",
|
||||
INIT_33 => X"{INIT_33}",
|
||||
INIT_34 => X"{INIT_34}",
|
||||
INIT_35 => X"{INIT_35}",
|
||||
INIT_36 => X"{INIT_36}",
|
||||
INIT_37 => X"{INIT_37}",
|
||||
INIT_38 => X"{INIT_38}",
|
||||
INIT_39 => X"{INIT_39}",
|
||||
INIT_3A => X"{INIT_3A}",
|
||||
INIT_3B => X"{INIT_3B}",
|
||||
INIT_3C => X"{INIT_3C}",
|
||||
INIT_3D => X"{INIT_3D}",
|
||||
INIT_3E => X"{INIT_3E}",
|
||||
INIT_3F => X"{INIT_3F}",
|
||||
INITP_00 => X"{INITP_00}",
|
||||
INITP_01 => X"{INITP_01}",
|
||||
INITP_02 => X"{INITP_02}",
|
||||
INITP_03 => X"{INITP_03}",
|
||||
INITP_04 => X"{INITP_04}",
|
||||
INITP_05 => X"{INITP_05}",
|
||||
INITP_06 => X"{INITP_06}",
|
||||
INITP_07 => X"{INITP_07}")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE {name}.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
|
||||
@@ -0,0 +1,92 @@
|
||||
component_name=uclock;
|
||||
width_a=18;
|
||||
depth_a=1024;
|
||||
configuration_port_a=read_only;
|
||||
port_a_enable_pin=false;
|
||||
port_a_handshaking_pins=false;
|
||||
port_a_register_inputs=false;
|
||||
port_a_init_pin=false;
|
||||
port_a_init_value=00000;
|
||||
port_a_additional_output_pipe_stages = 0;
|
||||
port_a_register_inputs = false;
|
||||
port_a_active_clock_edge = Rising_Edge_Triggered;
|
||||
width_b=18;
|
||||
depth_b=1024;
|
||||
configuration_port_b=read_and_write;
|
||||
write_mode_port_b=read_after_write;
|
||||
port_b_enable_pin=false;
|
||||
port_b_handshaking_pins=false;
|
||||
port_b_register_inputs=false;
|
||||
port_b_init_pin=false;
|
||||
port_b_init_value=00000;
|
||||
port_b_additional_output_pipe_stages = 0;
|
||||
port_b_register_inputs = false;
|
||||
port_b_active_clock_edge = Rising_Edge_Triggered;
|
||||
port_b_write_enable_polarity = Active_High;
|
||||
memory_initialization_radix=16;
|
||||
global_init_value=00000;
|
||||
memory_initialization_vector=
|
||||
00000, 2E000, 2E001, 2E002, 2E003, 2E004, 2E005, 2E006, 2E007, 2E008, 2E009, 2E00A, 2E00B, 2E00C, 300A4, 00D00,
|
||||
00C00, 3C001, 30115, 300C3, 00120, 30091, 1400D, 35012, 14054, 3501E, 14041, 35037, 300ED, 35012, 30091, 14049,
|
||||
3541C, 30091, 1404D, 3541C, 30091, 14045, 3541C, 30091, 1400D, 3542C, 300A8, 34012, 14020, 3541C, 3006D, 35812,
|
||||
2E606, 2E507, 2E408, 2E004, 2E005, 300A8, 34012, 30091, 1404C, 3541C, 30091, 14041, 3541C, 30091, 14052, 3541C,
|
||||
30091, 1404D, 3541C, 30091, 1400D, 35448, 300AC, 34012, 14020, 3541C, 30091, 1404F, 35055, 1C101, 3006D, 35812,
|
||||
2E609, 2E50A, 2E40B, 300AC, 34012, 30091, 1404E, 35460, 30091, 1400D, 3541C, 0600C, 0C002, 2E00C, 300AC, 34012,
|
||||
14046, 3541C, 30091, 14046, 3541C, 30091, 1400D, 3541C, 00000, 2E00C, 300A4, 300AC, 34012, 301EC, 3588B, 01620,
|
||||
18101, 30091, 1403A, 3548B, 301EC, 3588B, 01520, 18101, 30091, 1403A, 3548B, 301EC, 3588B, 01420, 18101, 30091,
|
||||
1400D, 3548B, 14618, 35C8B, 1453C, 35C8B, 1443C, 35C8B, 00000, 2000E, 2A000, 30125, 300E7, 30134, 00001, 2000E,
|
||||
2A000, 07010, 301E2, 18101, 2A000, 04000, 12010, 3549A, 30185, 34095, 04F01, 3009D, 2A000, 04000, 12002, 350A2,
|
||||
30185, 3409D, 2CF01, 2A000, 0600C, 0A001, 2C000, 2A000, 00E06, 30160, 300BC, 2A000, 00E09, 30160, 300BC, 3013D,
|
||||
300E7, 0600C, 12001, 350B6, 30153, 2A000, 12002, 350BA, 3014E, 2A000, 30148, 2A000, 00120, 07F10, 3009D, 14F0D,
|
||||
2B000, 18101, 340BD, 00120, 01210, 18210, 04000, 12008, 354DB, 30095, 2FF10, 14F0D, 2B000, 14F08, 350D3, 18101,
|
||||
15120, 354C6, 300EA, 1C101, 14120, 358D9, 300E7, 300EA, 340C6, 30122, 340C3, 300E4, 2EF20, 300FA, 300E4, 04000,
|
||||
12010, 2B000, 04F01, 340DF, 00F0D, 3009D, 2A000, 00F20, 3009D, 2A000, 00F08, 3009D, 2A000, 00F53, 3009D, 00F79,
|
||||
3009D, 00F6E, 3009D, 00F74, 3009D, 00F61, 3009D, 00F78, 3009D, 3410A, 00F4F, 3009D, 00F76, 3009D, 00F65, 3009D,
|
||||
00F72, 3009D, 00F66, 3009D, 00F6C, 3009D, 00F6F, 3009D, 00F77, 3009D, 300E7, 00F45, 3009D, 00F72, 3009D, 3009D,
|
||||
00F6F, 3009D, 00F72, 3009D, 2A000, 300E4, 00F4B, 3009D, 00F43, 3009D, 00F50, 3009D, 00F53, 3009D, 00F4D, 3009D,
|
||||
00F33, 3009D, 00F3E, 3009D, 2A000, 00F49, 3009D, 00F6E, 3009D, 00F76, 3009D, 00F61, 3009D, 00F6C, 3009D, 00F69,
|
||||
3009D, 00F64, 3009D, 2A000, 00F54, 3009D, 00F69, 3009D, 00F6D, 3009D, 00F65, 3009D, 2A000, 00F41, 3009D, 00F6C,
|
||||
3009D, 00F61, 3009D, 00F72, 3009D, 00F6D, 3009D, 2A000, 00F4F, 3009D, 00F46, 3009D, 3009D, 2A000, 00F4F, 3009D,
|
||||
00F4E, 3009D, 2A000, 00F41, 3009D, 00F63, 3009D, 00F74, 3009D, 00F69, 3009D, 00F76, 3009D, 00F65, 3009D, 2A000,
|
||||
00220, 070E0, 3017E, 2F120, 18201, 2F020, 18201, 0003A, 2F020, 18201, 18E01, 070E0, 3017E, 2F120, 18201, 2F020,
|
||||
18201, 0003A, 2F020, 18201, 18E01, 070E0, 3017E, 2F120, 18201, 2F020, 18201, 0000D, 2F020, 2A000, 00130, 18101,
|
||||
1C00A, 35D7F, 1C101, 1803A, 2A000, 2E010, 2E111, 2E212, 2E313, 2E414, 2E515, 06200, 06301, 3C000, 2ED00, 2EC01,
|
||||
3C001, 06400, 06501, 1D420, 1F530, 06202, 06303, 19240, 1B350, 00000, 1C2E8, 1E303, 3599F, 18001, 3419A, 182E8,
|
||||
1A303, 2E202, 2E303, 06204, 06305, 19200, 1A300, 00000, 1C2E8, 1E303, 359AD, 18001, 341AF, 182E8, 1A303, 2E204,
|
||||
2E305, 06108, 19100, 1413C, 351B7, 2E108, 341C9, 00100, 2E108, 06107, 18101, 1413C, 351BF, 2E107, 341C9, 00100,
|
||||
2E107, 06106, 18101, 14118, 351C7, 2E106, 341C9, 00100, 2E106, 06006, 06109, 15010, 355DB, 06007, 0610A, 15010,
|
||||
355DB, 06008, 0610B, 15010, 355DB, 0600C, 12002, 351DB, 0C001, 2E00C, 300A4, 06010, 06111, 06212, 06313, 06414,
|
||||
06515, 2A000, 14061, 2B800, 1407B, 2BC00, 0A0DF, 2A000, 180C6, 2B800, 1C0F6, 2A000, 07010, 301E8, 2B800, 01200,
|
||||
20206, 20206, 19200, 20206, 18101, 07010, 301E8, 2B800, 19200, 2A000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000,
|
||||
00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 00000, 18D01, 1AC00, 38001, 343FC;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,69 @@
|
||||
function bits = fill_uclock_program_store()
|
||||
bits = [ ...
|
||||
0, 188416, 188417, 188418, 188419, 188420, 188421, 188422, 188423, 188424, 188425, 188426, 188427, 188428, 196772, 3328, ...
|
||||
3072, 245761, 196885, 196803, 288, 196753, 81933, 217106, 82004, 217118, 81985, 217143, 196845, 217106, 196753, 81993, ...
|
||||
218140, 196753, 81997, 218140, 196753, 81989, 218140, 196753, 81933, 218156, 196776, 213010, 81952, 218140, 196717, 219154, ...
|
||||
189958, 189703, 189448, 188420, 188421, 196776, 213010, 196753, 81996, 218140, 196753, 81985, 218140, 196753, 82002, 218140, ...
|
||||
196753, 81997, 218140, 196753, 81933, 218184, 196780, 213010, 81952, 218140, 196753, 81999, 217173, 114945, 196717, 219154, ...
|
||||
189961, 189706, 189451, 196780, 213010, 196753, 81998, 218208, 196753, 81933, 218140, 24588, 49154, 188428, 196780, 213010, ...
|
||||
81990, 218140, 196753, 81990, 218140, 196753, 81933, 218140, 0, 188428, 196772, 196780, 213010, 197100, 219275, 5664, ...
|
||||
98561, 196753, 81978, 218251, 197100, 219275, 5408, 98561, 196753, 81978, 218251, 197100, 219275, 5152, 98561, 196753, ...
|
||||
81933, 218251, 83480, 220299, 83260, 220299, 83004, 220299, 0, 131086, 172032, 196901, 196839, 196916, 1, 131086, ...
|
||||
172032, 28688, 197090, 98561, 172032, 16384, 73744, 218266, 196997, 213141, 20225, 196765, 172032, 16384, 73730, 217250, ...
|
||||
196997, 213149, 184065, 172032, 24588, 40961, 180224, 172032, 3590, 196960, 196796, 172032, 3593, 196960, 196796, 196925, ...
|
||||
196839, 24588, 73729, 217270, 196947, 172032, 73730, 217274, 196942, 172032, 196936, 172032, 288, 32528, 196765, 85773, ...
|
||||
176128, 98561, 213181, 288, 4624, 98832, 16384, 73736, 218331, 196757, 196368, 85773, 176128, 85768, 217299, 98561, ...
|
||||
86304, 218310, 196842, 114945, 82208, 219353, 196839, 196842, 213190, 196898, 213187, 196836, 192288, 196858, 196836, 16384, ...
|
||||
73744, 176128, 20225, 213215, 3853, 196765, 172032, 3872, 196765, 172032, 3848, 196765, 172032, 3923, 196765, 3961, ...
|
||||
196765, 3950, 196765, 3956, 196765, 3937, 196765, 3960, 196765, 213258, 3919, 196765, 3958, 196765, 3941, 196765, ...
|
||||
3954, 196765, 3942, 196765, 3948, 196765, 3951, 196765, 3959, 196765, 196839, 3909, 196765, 3954, 196765, 196765, ...
|
||||
3951, 196765, 3954, 196765, 172032, 196836, 3915, 196765, 3907, 196765, 3920, 196765, 3923, 196765, 3917, 196765, ...
|
||||
3891, 196765, 3902, 196765, 172032, 3913, 196765, 3950, 196765, 3958, 196765, 3937, 196765, 3948, 196765, 3945, ...
|
||||
196765, 3940, 196765, 172032, 3924, 196765, 3945, 196765, 3949, 196765, 3941, 196765, 172032, 3905, 196765, 3948, ...
|
||||
196765, 3937, 196765, 3954, 196765, 3949, 196765, 172032, 3919, 196765, 3910, 196765, 196765, 172032, 3919, 196765, ...
|
||||
3918, 196765, 172032, 3905, 196765, 3939, 196765, 3956, 196765, 3945, 196765, 3958, 196765, 3941, 196765, 172032, ...
|
||||
544, 28896, 196990, 192800, 98817, 192544, 98817, 58, 192544, 98817, 101889, 28896, 196990, 192800, 98817, 192544, ...
|
||||
98817, 58, 192544, 98817, 101889, 28896, 196990, 192800, 98817, 192544, 98817, 13, 192544, 172032, 304, 98561, ...
|
||||
114698, 220543, 114945, 98362, 172032, 188432, 188689, 188946, 189203, 189460, 189717, 25088, 25345, 245760, 191744, 191489, ...
|
||||
245761, 25600, 25857, 119840, 128304, 25090, 25347, 102976, 111440, 0, 115432, 123651, 219551, 98305, 213402, 99048, ...
|
||||
107267, 188930, 189187, 25092, 25349, 102912, 107264, 0, 115432, 123651, 219565, 98305, 213423, 99048, 107267, 188932, ...
|
||||
189189, 24840, 102656, 82236, 217527, 188680, 213449, 256, 188680, 24839, 98561, 82236, 217535, 188679, 213449, 256, ...
|
||||
188679, 24838, 98561, 82200, 217543, 188678, 213449, 256, 188678, 24582, 24841, 86032, 218587, 24583, 24842, 86032, ...
|
||||
218587, 24584, 24843, 86032, 218587, 24588, 73730, 217563, 49153, 188428, 196772, 24592, 24849, 25106, 25363, 25620, ...
|
||||
25877, 172032, 82017, 178176, 82043, 179200, 41183, 172032, 98502, 178176, 114934, 172032, 28688, 197096, 178176, 4608, ...
|
||||
131590, 131590, 102912, 131590, 98561, 28688, 197096, 178176, 102912, 172032, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ...
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 101633, 109568, 229377, 214012, ...
|
||||
];
|
||||
|
||||
return;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,262 @@
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// Copyright (c) 2004 Xilinx, Inc.
|
||||
// All Rights Reserved
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// ____ ____
|
||||
// / /\/ /
|
||||
// /___/ \ / Vendor: Xilinx
|
||||
// \ \ \/ Version: v1.30
|
||||
// \ \ Application : KCPSM3
|
||||
// / / Filename: uclock.v
|
||||
// /___/ /\
|
||||
// \ \ / \
|
||||
// \___\/\___\
|
||||
//
|
||||
//Command: kcpsm3 uclock.psm
|
||||
//Device: Spartan-3, Spartan-3E, Virtex-II, and Virtex-II Pro FPGAs
|
||||
//Design Name: uclock
|
||||
//Generated 25Sep2005-15:52:57.
|
||||
//Purpose:
|
||||
// uclock verilog program definition.
|
||||
//
|
||||
//Reference:
|
||||
// PicoBlaze 8-bit Embedded Microcontroller User Guide
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1 ps / 1ps
|
||||
module uclock (address, instruction, clk);
|
||||
input [9:0] address;
|
||||
input clk;
|
||||
output [17:0] instruction;
|
||||
RAMB16_S18 ram_1024_x_18(
|
||||
.DI (16'h0000),
|
||||
.DIP (2'b00),
|
||||
.EN (1'b1),
|
||||
.WE (1'b0),
|
||||
.SSR (1'b0),
|
||||
.CLK (clk),
|
||||
.ADDR (address),
|
||||
.DO (instruction[15:0]),
|
||||
.DOP (instruction[17:16]))
|
||||
/*synthesis
|
||||
init_00 = "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000"
|
||||
init_01 = "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00"
|
||||
init_02 = "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C"
|
||||
init_03 = "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606"
|
||||
init_04 = "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091"
|
||||
init_05 = "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609"
|
||||
init_06 = "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046"
|
||||
init_07 = "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101"
|
||||
init_08 = "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D"
|
||||
init_09 = "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000"
|
||||
init_0A = "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185"
|
||||
init_0B = "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7"
|
||||
init_0C = "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000"
|
||||
init_0D = "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120"
|
||||
init_0E = "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010"
|
||||
init_0F = "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D"
|
||||
init_10 = "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72"
|
||||
init_11 = "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F"
|
||||
init_12 = "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33"
|
||||
init_13 = "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D"
|
||||
init_14 = "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D"
|
||||
init_15 = "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E"
|
||||
init_16 = "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220"
|
||||
init_17 = "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201"
|
||||
init_18 = "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A"
|
||||
init_19 = "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001"
|
||||
init_1A = "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303"
|
||||
init_1B = "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305"
|
||||
init_1C = "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107"
|
||||
init_1D = "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB"
|
||||
init_1E = "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515"
|
||||
init_1F = "000000000000000000000000A0009200B80001E8701081010206920002060206"
|
||||
init_20 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_21 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_22 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_23 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_24 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_25 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_26 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_27 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_28 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_29 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_2F = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_30 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_31 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_32 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_33 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_34 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_35 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_36 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_37 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_38 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_39 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3A = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3B = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3C = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3D = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3E = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
init_3F = "43FC8001AC008D01000000000000000000000000000000000000000000000000"
|
||||
initp_00 = "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8"
|
||||
initp_01 = "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD"
|
||||
initp_02 = "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC"
|
||||
initp_03 = "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D"
|
||||
initp_04 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_05 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_06 = "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
initp_07 = "F500000000000000000000000000000000000000000000000000000000000000" */;
|
||||
// synthesis translate_off
|
||||
// Attributes for Simulation
|
||||
defparam ram_1024_x_18.INIT_00 = 256'h0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000;
|
||||
defparam ram_1024_x_18.INIT_01 = 256'h40490091501200ED50374041501E40545012400D0091012000C30115C0010C00;
|
||||
defparam ram_1024_x_18.INIT_02 = 256'h5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C;
|
||||
defparam ram_1024_x_18.INIT_03 = 256'h541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606;
|
||||
defparam ram_1024_x_18.INIT_04 = 256'h5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091;
|
||||
defparam ram_1024_x_18.INIT_05 = 256'h401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609;
|
||||
defparam ram_1024_x_18.INIT_06 = 256'h1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046;
|
||||
defparam ram_1024_x_18.INIT_07 = 256'h009181011420588B01EC548B403A009181011520588B01EC548B403A00918101;
|
||||
defparam ram_1024_x_18.INIT_08 = 256'h000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D;
|
||||
defparam ram_1024_x_18.INIT_09 = 256'h50A220024000A000009D4F0140950185549A20104000A000810101E27010A000;
|
||||
defparam ram_1024_x_18.INIT_0A = 256'h013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185;
|
||||
defparam ram_1024_x_18.INIT_0B = 256'h4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7;
|
||||
defparam ram_1024_x_18.INIT_0C = 256'h810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000;
|
||||
defparam ram_1024_x_18.INIT_0D = 256'h400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120;
|
||||
defparam ram_1024_x_18.INIT_0E = 256'h0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010;
|
||||
defparam ram_1024_x_18.INIT_0F = 256'h009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D;
|
||||
defparam ram_1024_x_18.INIT_10 = 256'h009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72;
|
||||
defparam ram_1024_x_18.INIT_11 = 256'h009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F;
|
||||
defparam ram_1024_x_18.INIT_12 = 256'h0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33;
|
||||
defparam ram_1024_x_18.INIT_13 = 256'h0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D;
|
||||
defparam ram_1024_x_18.INIT_14 = 256'h009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D;
|
||||
defparam ram_1024_x_18.INIT_15 = 256'hA000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E;
|
||||
defparam ram_1024_x_18.INIT_16 = 256'hF0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220;
|
||||
defparam ram_1024_x_18.INIT_17 = 256'h81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201;
|
||||
defparam ram_1024_x_18.INIT_18 = 256'hEC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A;
|
||||
defparam ram_1024_x_18.INIT_19 = 256'h82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001;
|
||||
defparam ram_1024_x_18.INIT_1A = 256'hE204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303;
|
||||
defparam ram_1024_x_18.INIT_1B = 256'h010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305;
|
||||
defparam ram_1024_x_18.INIT_1C = 256'h5010610A600755DB501061096006E106010041C9E10651C7411881016106E107;
|
||||
defparam ram_1024_x_18.INIT_1D = 256'h6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB;
|
||||
defparam ram_1024_x_18.INIT_1E = 256'h1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515;
|
||||
defparam ram_1024_x_18.INIT_1F = 256'h000000000000000000000000A0009200B80001E8701081010206920002060206;
|
||||
defparam ram_1024_x_18.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INIT_3F = 256'h43FC8001AC008D01000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_00 = 256'hD3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8;
|
||||
defparam ram_1024_x_18.INITP_01 = 256'hCCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD;
|
||||
defparam ram_1024_x_18.INITP_02 = 256'h4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC;
|
||||
defparam ram_1024_x_18.INITP_03 = 256'h0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D;
|
||||
defparam ram_1024_x_18.INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
|
||||
defparam ram_1024_x_18.INITP_07 = 256'hF500000000000000000000000000000000000000000000000000000000000000;
|
||||
// synthesis translate_on
|
||||
// Attributes for XST (Synplicity attributes are in-line)
|
||||
// synthesis attribute INIT_00 of ram_1024_x_18 is "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000"
|
||||
// synthesis attribute INIT_01 of ram_1024_x_18 is "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00"
|
||||
// synthesis attribute INIT_02 of ram_1024_x_18 is "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C"
|
||||
// synthesis attribute INIT_03 of ram_1024_x_18 is "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606"
|
||||
// synthesis attribute INIT_04 of ram_1024_x_18 is "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091"
|
||||
// synthesis attribute INIT_05 of ram_1024_x_18 is "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609"
|
||||
// synthesis attribute INIT_06 of ram_1024_x_18 is "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046"
|
||||
// synthesis attribute INIT_07 of ram_1024_x_18 is "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101"
|
||||
// synthesis attribute INIT_08 of ram_1024_x_18 is "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D"
|
||||
// synthesis attribute INIT_09 of ram_1024_x_18 is "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000"
|
||||
// synthesis attribute INIT_0A of ram_1024_x_18 is "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185"
|
||||
// synthesis attribute INIT_0B of ram_1024_x_18 is "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7"
|
||||
// synthesis attribute INIT_0C of ram_1024_x_18 is "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000"
|
||||
// synthesis attribute INIT_0D of ram_1024_x_18 is "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120"
|
||||
// synthesis attribute INIT_0E of ram_1024_x_18 is "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010"
|
||||
// synthesis attribute INIT_0F of ram_1024_x_18 is "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D"
|
||||
// synthesis attribute INIT_10 of ram_1024_x_18 is "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72"
|
||||
// synthesis attribute INIT_11 of ram_1024_x_18 is "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F"
|
||||
// synthesis attribute INIT_12 of ram_1024_x_18 is "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33"
|
||||
// synthesis attribute INIT_13 of ram_1024_x_18 is "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D"
|
||||
// synthesis attribute INIT_14 of ram_1024_x_18 is "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D"
|
||||
// synthesis attribute INIT_15 of ram_1024_x_18 is "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E"
|
||||
// synthesis attribute INIT_16 of ram_1024_x_18 is "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220"
|
||||
// synthesis attribute INIT_17 of ram_1024_x_18 is "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201"
|
||||
// synthesis attribute INIT_18 of ram_1024_x_18 is "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A"
|
||||
// synthesis attribute INIT_19 of ram_1024_x_18 is "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001"
|
||||
// synthesis attribute INIT_1A of ram_1024_x_18 is "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303"
|
||||
// synthesis attribute INIT_1B of ram_1024_x_18 is "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305"
|
||||
// synthesis attribute INIT_1C of ram_1024_x_18 is "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107"
|
||||
// synthesis attribute INIT_1D of ram_1024_x_18 is "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB"
|
||||
// synthesis attribute INIT_1E of ram_1024_x_18 is "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515"
|
||||
// synthesis attribute INIT_1F of ram_1024_x_18 is "000000000000000000000000A0009200B80001E8701081010206920002060206"
|
||||
// synthesis attribute INIT_20 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_21 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_22 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_23 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_24 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_25 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_26 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_27 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_28 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_29 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_2F of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_30 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_31 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_32 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_33 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_34 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_35 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_36 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_37 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_38 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_39 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3A of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3B of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3C of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3D of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3E of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INIT_3F of ram_1024_x_18 is "43FC8001AC008D01000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_00 of ram_1024_x_18 is "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8"
|
||||
// synthesis attribute INITP_01 of ram_1024_x_18 is "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD"
|
||||
// synthesis attribute INITP_02 of ram_1024_x_18 is "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC"
|
||||
// synthesis attribute INITP_03 of ram_1024_x_18 is "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D"
|
||||
// synthesis attribute INITP_04 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_05 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_06 of ram_1024_x_18 is "0000000000000000000000000000000000000000000000000000000000000000"
|
||||
// synthesis attribute INITP_07 of ram_1024_x_18 is "F500000000000000000000000000000000000000000000000000000000000000"
|
||||
endmodule
|
||||
// END OF FILE uclock.v
|
||||
@@ -0,0 +1,274 @@
|
||||
--
|
||||
-- Definition of a single port ROM for KCPSM3 program defined by uclock.psm
|
||||
--
|
||||
-- Generated by KCPSM3 Assembler 25Sep2005-15:52:57.
|
||||
--
|
||||
-- Standard IEEE libraries
|
||||
--
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
--
|
||||
-- The Unisim Library is used to define Xilinx primitives. It is also used during
|
||||
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
|
||||
--
|
||||
library unisim;
|
||||
use unisim.vcomponents.all;
|
||||
--
|
||||
--
|
||||
entity uclock is
|
||||
Port ( address : in std_logic_vector(9 downto 0);
|
||||
instruction : out std_logic_vector(17 downto 0);
|
||||
clk : in std_logic);
|
||||
end uclock;
|
||||
--
|
||||
architecture low_level_definition of uclock is
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
-- The information is repeated in the generic map for functional simulation
|
||||
--
|
||||
attribute INIT_00 : string;
|
||||
attribute INIT_01 : string;
|
||||
attribute INIT_02 : string;
|
||||
attribute INIT_03 : string;
|
||||
attribute INIT_04 : string;
|
||||
attribute INIT_05 : string;
|
||||
attribute INIT_06 : string;
|
||||
attribute INIT_07 : string;
|
||||
attribute INIT_08 : string;
|
||||
attribute INIT_09 : string;
|
||||
attribute INIT_0A : string;
|
||||
attribute INIT_0B : string;
|
||||
attribute INIT_0C : string;
|
||||
attribute INIT_0D : string;
|
||||
attribute INIT_0E : string;
|
||||
attribute INIT_0F : string;
|
||||
attribute INIT_10 : string;
|
||||
attribute INIT_11 : string;
|
||||
attribute INIT_12 : string;
|
||||
attribute INIT_13 : string;
|
||||
attribute INIT_14 : string;
|
||||
attribute INIT_15 : string;
|
||||
attribute INIT_16 : string;
|
||||
attribute INIT_17 : string;
|
||||
attribute INIT_18 : string;
|
||||
attribute INIT_19 : string;
|
||||
attribute INIT_1A : string;
|
||||
attribute INIT_1B : string;
|
||||
attribute INIT_1C : string;
|
||||
attribute INIT_1D : string;
|
||||
attribute INIT_1E : string;
|
||||
attribute INIT_1F : string;
|
||||
attribute INIT_20 : string;
|
||||
attribute INIT_21 : string;
|
||||
attribute INIT_22 : string;
|
||||
attribute INIT_23 : string;
|
||||
attribute INIT_24 : string;
|
||||
attribute INIT_25 : string;
|
||||
attribute INIT_26 : string;
|
||||
attribute INIT_27 : string;
|
||||
attribute INIT_28 : string;
|
||||
attribute INIT_29 : string;
|
||||
attribute INIT_2A : string;
|
||||
attribute INIT_2B : string;
|
||||
attribute INIT_2C : string;
|
||||
attribute INIT_2D : string;
|
||||
attribute INIT_2E : string;
|
||||
attribute INIT_2F : string;
|
||||
attribute INIT_30 : string;
|
||||
attribute INIT_31 : string;
|
||||
attribute INIT_32 : string;
|
||||
attribute INIT_33 : string;
|
||||
attribute INIT_34 : string;
|
||||
attribute INIT_35 : string;
|
||||
attribute INIT_36 : string;
|
||||
attribute INIT_37 : string;
|
||||
attribute INIT_38 : string;
|
||||
attribute INIT_39 : string;
|
||||
attribute INIT_3A : string;
|
||||
attribute INIT_3B : string;
|
||||
attribute INIT_3C : string;
|
||||
attribute INIT_3D : string;
|
||||
attribute INIT_3E : string;
|
||||
attribute INIT_3F : string;
|
||||
attribute INITP_00 : string;
|
||||
attribute INITP_01 : string;
|
||||
attribute INITP_02 : string;
|
||||
attribute INITP_03 : string;
|
||||
attribute INITP_04 : string;
|
||||
attribute INITP_05 : string;
|
||||
attribute INITP_06 : string;
|
||||
attribute INITP_07 : string;
|
||||
--
|
||||
-- Attributes to define ROM contents during implementation synthesis.
|
||||
--
|
||||
attribute INIT_00 of ram_1024_x_18 : label is "0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000";
|
||||
attribute INIT_01 of ram_1024_x_18 : label is "40490091501200ED50374041501E40545012400D0091012000C30115C0010C00";
|
||||
attribute INIT_02 of ram_1024_x_18 : label is "5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C";
|
||||
attribute INIT_03 of ram_1024_x_18 : label is "541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606";
|
||||
attribute INIT_04 of ram_1024_x_18 : label is "5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091";
|
||||
attribute INIT_05 of ram_1024_x_18 : label is "401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609";
|
||||
attribute INIT_06 of ram_1024_x_18 : label is "1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046";
|
||||
attribute INIT_07 of ram_1024_x_18 : label is "009181011420588B01EC548B403A009181011520588B01EC548B403A00918101";
|
||||
attribute INIT_08 of ram_1024_x_18 : label is "000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D";
|
||||
attribute INIT_09 of ram_1024_x_18 : label is "50A220024000A000009D4F0140950185549A20104000A000810101E27010A000";
|
||||
attribute INIT_0A of ram_1024_x_18 : label is "013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185";
|
||||
attribute INIT_0B of ram_1024_x_18 : label is "4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7";
|
||||
attribute INIT_0C of ram_1024_x_18 : label is "810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000";
|
||||
attribute INIT_0D of ram_1024_x_18 : label is "400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120";
|
||||
attribute INIT_0E of ram_1024_x_18 : label is "0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010";
|
||||
attribute INIT_0F of ram_1024_x_18 : label is "009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D";
|
||||
attribute INIT_10 of ram_1024_x_18 : label is "009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72";
|
||||
attribute INIT_11 of ram_1024_x_18 : label is "009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F";
|
||||
attribute INIT_12 of ram_1024_x_18 : label is "0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33";
|
||||
attribute INIT_13 of ram_1024_x_18 : label is "0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D";
|
||||
attribute INIT_14 of ram_1024_x_18 : label is "009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D";
|
||||
attribute INIT_15 of ram_1024_x_18 : label is "A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E";
|
||||
attribute INIT_16 of ram_1024_x_18 : label is "F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220";
|
||||
attribute INIT_17 of ram_1024_x_18 : label is "81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201";
|
||||
attribute INIT_18 of ram_1024_x_18 : label is "EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A";
|
||||
attribute INIT_19 of ram_1024_x_18 : label is "82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001";
|
||||
attribute INIT_1A of ram_1024_x_18 : label is "E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303";
|
||||
attribute INIT_1B of ram_1024_x_18 : label is "010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305";
|
||||
attribute INIT_1C of ram_1024_x_18 : label is "5010610A600755DB501061096006E106010041C9E10651C7411881016106E107";
|
||||
attribute INIT_1D of ram_1024_x_18 : label is "6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB";
|
||||
attribute INIT_1E of ram_1024_x_18 : label is "1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515";
|
||||
attribute INIT_1F of ram_1024_x_18 : label is "000000000000000000000000A0009200B80001E8701081010206920002060206";
|
||||
attribute INIT_20 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_21 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_22 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_23 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_24 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_25 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_26 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_27 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_28 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_29 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_2F of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_30 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_31 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_32 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_33 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_34 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_35 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_36 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_37 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_38 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_39 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3A of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3B of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3C of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3D of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3E of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INIT_3F of ram_1024_x_18 : label is "43FC8001AC008D01000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_00 of ram_1024_x_18 : label is "D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8";
|
||||
attribute INITP_01 of ram_1024_x_18 : label is "CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD";
|
||||
attribute INITP_02 of ram_1024_x_18 : label is "4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC";
|
||||
attribute INITP_03 of ram_1024_x_18 : label is "0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D";
|
||||
attribute INITP_04 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_05 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_06 of ram_1024_x_18 : label is "0000000000000000000000000000000000000000000000000000000000000000";
|
||||
attribute INITP_07 of ram_1024_x_18 : label is "F500000000000000000000000000000000000000000000000000000000000000";
|
||||
--
|
||||
begin
|
||||
--
|
||||
--Instantiate the Xilinx primitive for a block RAM
|
||||
ram_1024_x_18: RAMB16_S18
|
||||
--synthesis translate_off
|
||||
--INIT values repeated to define contents for functional simulation
|
||||
generic map ( INIT_00 => X"0D0000A4E00CE00BE00AE009E008E007E006E005E004E003E002E001E0000000",
|
||||
INIT_01 => X"40490091501200ED50374041501E40545012400D0091012000C30115C0010C00",
|
||||
INIT_02 => X"5812006D541C4020401200A8542C400D0091541C40450091541C404D0091541C",
|
||||
INIT_03 => X"541C40520091541C40410091541C404C0091401200A8E005E004E408E507E606",
|
||||
INIT_04 => X"5812006DC1015055404F0091541C4020401200AC5448400D0091541C404D0091",
|
||||
INIT_05 => X"401200ACE00CC002600C541C400D00915460404E0091401200ACE40BE50AE609",
|
||||
INIT_06 => X"1620588B01EC401200AC00A4E00C0000541C400D0091541C40460091541C4046",
|
||||
INIT_07 => X"009181011420588B01EC548B403A009181011520588B01EC548B403A00918101",
|
||||
INIT_08 => X"000E0001013400E70125A000000E00005C8B443C5C8B453C5C8B4618548B400D",
|
||||
INIT_09 => X"50A220024000A000009D4F0140950185549A20104000A000810101E27010A000",
|
||||
INIT_0A => X"013D00BC01600E09A00000BC01600E06A000C000A001600CA000CF01409D0185",
|
||||
INIT_0B => X"4F0D009D7F100120A0000148A000014E50BA2002A000015350B62001600C00E7",
|
||||
INIT_0C => X"810150D34F08B0004F0DFF10009554DB2008400082101210012040BD8101B000",
|
||||
INIT_0D => X"400000E400FAEF2000E440C3012240C600EA00E758D94120C10100EA54C65120",
|
||||
INIT_0E => X"0F79009D0F53A000009D0F08A000009D0F20A000009D0F0D40DF4F01B0002010",
|
||||
INIT_0F => X"009D0F65009D0F76009D0F4F410A009D0F78009D0F61009D0F74009D0F6E009D",
|
||||
INIT_10 => X"009D009D0F72009D0F4500E7009D0F77009D0F6F009D0F6C009D0F66009D0F72",
|
||||
INIT_11 => X"009D0F4D009D0F53009D0F50009D0F43009D0F4B00E4A000009D0F72009D0F6F",
|
||||
INIT_12 => X"0F69009D0F6C009D0F61009D0F76009D0F6E009D0F49A000009D0F3E009D0F33",
|
||||
INIT_13 => X"0F6C009D0F41A000009D0F65009D0F6D009D0F69009D0F54A000009D0F64009D",
|
||||
INIT_14 => X"009D0F4FA000009D009D0F46009D0F4FA000009D0F6D009D0F72009D0F61009D",
|
||||
INIT_15 => X"A000009D0F65009D0F76009D0F69009D0F74009D0F63009D0F41A000009D0F4E",
|
||||
INIT_16 => X"F0208201F120017E70E08E018201F020003A8201F0208201F120017E70E00220",
|
||||
INIT_17 => X"81010130A000F020000D8201F0208201F120017E70E08E018201F020003A8201",
|
||||
INIT_18 => X"EC01ED00C00063016200E515E414E313E212E111E010A000803AC1015D7FC00A",
|
||||
INIT_19 => X"82E8419A8001599FE303C2E80000B350924063036202F530D42065016400C001",
|
||||
INIT_1A => X"E204A30382E841AF800159ADE303C2E80000A300920063056204E303E202A303",
|
||||
INIT_1B => X"010041C9E10751BF413C81016107E108010041C9E10851B7413C91006108E305",
|
||||
INIT_1C => X"5010610A600755DB501061096006E106010041C9E10651C7411881016106E107",
|
||||
INIT_1D => X"6414631362126111601000A4E00CC00151DB2002600C55DB5010610B600855DB",
|
||||
INIT_1E => X"1200B80001E87010A000C0F6B80080C6A000A0DFBC00407BB8004061A0006515",
|
||||
INIT_1F => X"000000000000000000000000A0009200B80001E8701081010206920002060206",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"43FC8001AC008D01000000000000000000000000000000000000000000000000",
|
||||
INITP_00 => X"D3F74FDD3FF8DF7DF837DFEAF77DFDF7DF7DFEAAFDFDF7DF7FDDDCFC3AAAAAA8",
|
||||
INITP_01 => X"CCCF333332CB2CC93EFFFD7D766F443670BBDBD3FCBCA0AFD2CFD2728FE8DDDD",
|
||||
INITP_02 => X"4A19B1619B1619B0B333332CCBCCB33332CCCCB3333332CCCCCCCECCF33CCCCC",
|
||||
INITP_03 => X"0009B19A2C9989980038D34343423B523B523B529775142977514143AC2AAA5D",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"F500000000000000000000000000000000000000000000000000000000000000")
|
||||
--synthesis translate_on
|
||||
port map( DI => "0000000000000000",
|
||||
DIP => "00",
|
||||
EN => '1',
|
||||
WE => '0',
|
||||
SSR => '0',
|
||||
CLK => clk,
|
||||
ADDR => address,
|
||||
DO => instruction(15 downto 0),
|
||||
DOP => instruction(17 downto 16));
|
||||
--
|
||||
end low_level_definition;
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
--
|
||||
-- END OF FILE uclock.vhd
|
||||
--
|
||||
------------------------------------------------------------------------------------
|
||||
@@ -0,0 +1,3 @@
|
||||
copy %1.psm previous_%1.psm
|
||||
del %1.psm
|
||||
copy %1.fmt %1.psm
|
||||
@@ -0,0 +1,25 @@
|
||||
;Interrupt example
|
||||
;
|
||||
CONSTANT waveform_port, 02 ;bit0 will be data
|
||||
CONSTANT counter_port, 04
|
||||
CONSTANT pattern_10101010, AA
|
||||
NAMEREG sA, interrupt_counter
|
||||
;
|
||||
start: LOAD interrupt_counter, 00 ;reset interrupt counter
|
||||
LOAD s2, pattern_10101010 ;initial output condition
|
||||
ENABLE INTERRUPT
|
||||
;
|
||||
drive_wave: OUTPUT s2, waveform_port
|
||||
LOAD s0, 07 ;delay size
|
||||
loop: SUB s0, 01 ;delay loop
|
||||
JUMP NZ, loop
|
||||
XOR s2, FF ;toggle waveform
|
||||
JUMP drive_wave
|
||||
;
|
||||
ADDRESS 2B0
|
||||
int_routine: ADD interrupt_counter, 01 ;increment counter
|
||||
OUTPUT interrupt_counter, counter_port
|
||||
RETURNI ENABLE
|
||||
;
|
||||
ADDRESS 3FF ;set interrupt vector
|
||||
JUMP int_routine
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user