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- writes have at least lead-in of one cycle if lead-in is speifified to 0

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- no data drive during lead-out
- no instant data drive in idle on 'en'
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git-svn-id: http://moon:8086/svn/vhdl/trunk@564 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-30 12:26:42 +00:00
parent 989fe72ddb
commit d5254aa0d7
1 changed files with 7 additions and 9 deletions
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lib/misc/async_port_wb.vhd
+7 -9
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@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.9 2009-10-30 10:49:15 Jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.10 2009-10-30 12:26:42 Jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -79,7 +79,7 @@ architecture Behavioral of async_port_wb is
SRDY_O <= CYC_I and rdyo; SRDY_O <= CYC_I and rdyo;
en <= CYC_I and STB_I; en <= CYC_I and STB_I;
do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = WE_I_r) and (WE_I = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0'; do_page_read <= '1' when (async_timespec.can_page_rd and (WE_I = '0') and (WE_I_r = '0') and (ADDR_I(addr_width-1 downto async_timespec.nbits_page_rd) = ADDR_I_r(addr_width-1 downto async_timespec.nbits_page_rd))) else '0';
proc_cycle_counter: proc_cycle_counter:
process(CLK_I) process(CLK_I)
@@ -141,9 +141,8 @@ architecture Behavioral of async_port_wb is
if async_timespec.ncyc_leadin = 0 then if async_timespec.ncyc_leadin = 0 then
sn <= pulse; sn <= pulse;
if WE_I = '1' then if WE_I = '1' then
cycle_reload <= async_timespec.ncyc_pulse_wr-1; cycle_reload <= 0;
as.wr <= '1'; sn <= leadin; -- always lead-in for writes
as.drive_d <= '1';
else else
cycle_reload <= async_timespec.ncyc_pulse_rd-1; cycle_reload <= async_timespec.ncyc_pulse_rd-1;
as.rd <= '1'; as.rd <= '1';
@@ -156,16 +155,16 @@ architecture Behavioral of async_port_wb is
when leadin => when leadin =>
as.cs <= '1'; as.cs <= '1';
as.rd <= not WE_I_r;
as.drive_d <= WE_I_r;
as.wr <= WE_I_r;
if cycle_cnt = 0 then if cycle_cnt = 0 then
cc_rst <= '1'; cc_rst <= '1';
sn <= pulse; sn <= pulse;
if WE_I_r = '1' then if WE_I_r = '1' then
cycle_reload <= async_timespec.ncyc_pulse_wr-1; cycle_reload <= async_timespec.ncyc_pulse_wr-1;
as.wr <= '1';
as.drive_d <= '1';
else else
cycle_reload <= async_timespec.ncyc_pulse_rd-1; cycle_reload <= async_timespec.ncyc_pulse_rd-1;
as.rd <= '1';
end if; end if;
end if; end if;
@@ -197,7 +196,6 @@ architecture Behavioral of async_port_wb is
when leadout => when leadout =>
as.cs <= '1'; as.cs <= '1';
as.drive_d <= WE_I_r;
if cycle_cnt = 0 then if cycle_cnt = 0 then
cc_rst <= '1'; cc_rst <= '1';
rdy <= '1'; rdy <= '1';