diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd
index e07ef2a..a2af1a2 100644
--- a/lib/misc/async_port_wb.vhd
+++ b/lib/misc/async_port_wb.vhd
@@ -1,5 +1,5 @@
 -----------------------------------------------------------------------
--- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.12 2009-11-02 10:29:23 Jens Exp $
+-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.13 2009-11-04 19:26:53 Jens Exp $
 -----------------------------------------------------------------------
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
@@ -251,7 +251,7 @@ architecture Behavioral of async_port_wb is
 				SEL_I_r		<= (others => '0');
 			elsif en = '1' and rdy = '1' then
 				async_a 	<= ADDR_I(addr_width-1 downto 0);
-				async_be	<= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I);
+				async_be	<= (byte_sel_width-1 downto 0 => not async_timespec.pol_be) xor ((byte_sel_width-1 downto 0 => as.cs) and SEL_I(byte_sel_width-1 downto 0));
 				SEL_I_r		<= SEL_I(byte_sel_width-1 downto 0);
 				if is_idle = '1' then
 					ADDR_I_r 	<= ADDR_I(addr_width-1 downto 0);