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- fixed rst

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- use main_sim for test bench

git-svn-id: http://moon:8086/svn/vhdl/trunk@1576 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 14:14:22 +00:00
parent c34cdf77ac
commit c1e96aecba
3 changed files with 16 additions and 13 deletions
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projects/vga_ctrl/ghdl/tb_vga_ctrl.make
+3 -3
View File
@@ -9,8 +9,8 @@ include $(LIB_PATH)/CPUs/JCpu/ghdl/jcpu_core.inc
SRCS += $(VGA_BACKEND_SRCS) SRCS += $(VGA_BACKEND_SRCS)
SRCS += $(FIFO_ASYNC_SRCS) SRCS += $(FIFO_ASYNC_SRCS)
SRCS += $(JCPU_CORE_SRCS) SRCS += $(JCPU_CORE_SRCS)
SRCS += ../src/main_xrom.vhdl SRCS += ../src/sim/main_sim_xrom.vhdl
SRCS += ../src/main_irom.vhdl SRCS += ../src/sim/main_sim_irom.vhdl
SRCS += ../src/cpu_embedded.vhd SRCS += ../src/cpu_embedded.vhd
SRCS += ../src/vga_ctrl_top.vhd SRCS += ../src/vga_ctrl_top.vhd
SRCS += ../src/tb_vga_ctrl.vhd SRCS += ../src/tb_vga_ctrl.vhd
@@ -19,7 +19,7 @@ SRCS += ../src/tb_vga_ctrl.vhd
# Compile # Compile
TARGET := tb_vga_ctrl TARGET := tb_vga_ctrl
ENTITY := tb_vga_ctrl ENTITY := tb_vga_ctrl
RUN_TIME := 250us RUN_TIME := 2500us
include $(VHDL_HOME)/make/ghdl.mk include $(VHDL_HOME)/make/ghdl.mk
# ----------------------------------------------------------- # -----------------------------------------------------------
projects/vga_ctrl/src/tb_vga_ctrl.vhd
+11 -8
View File
@@ -68,7 +68,10 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
END COMPONENT; END COMPONENT;
--Constants --Constants
constant tsvga : vga_timespec_t := ts_vga_testbench;
constant PERIOD : time := 10 ns; constant PERIOD : time := 10 ns;
constant SYS_CLK_PERIOD : time := 10 ns;
constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;
--Inputs --Inputs
SIGNAL sys_rst_in : std_logic := '1'; SIGNAL sys_rst_in : std_logic := '1';
@@ -100,7 +103,7 @@ BEGIN
uut: vga_ctrl_top uut: vga_ctrl_top
GENERIC MAP GENERIC MAP
( (
tsvga => ts_vga_testbench tsvga => tsvga
) )
PORT MAP PORT MAP
( (
@@ -123,32 +126,32 @@ BEGIN
sys_led => sys_led sys_led => sys_led
); );
tb_clk : PROCESS sys_clk : PROCESS
BEGIN BEGIN
sys_clk_in <= not sys_clk_in; sys_clk_in <= not sys_clk_in;
wait for PERIOD/2; wait for SYS_CLK_PERIOD/2;
END PROCESS; END PROCESS;
vga_clk : PROCESS vga_clk : PROCESS
BEGIN BEGIN
sys_vga_clk_in <= not sys_vga_clk_in; sys_vga_clk_in <= not sys_vga_clk_in;
wait for PERIOD/2; wait for VGA_CLK_PERIOD/2;
END PROCESS; END PROCESS;
tb : PROCESS tb : PROCESS
BEGIN BEGIN
-- Wait 100 ns for global reset to finish -- Wait 100 ns for global reset to finish
wait for 100*PERIOD; wait for 100*SYS_CLK_PERIOD;
sys_rst_in <= '0'; sys_rst_in <= '0';
wait for PERIOD; wait for SYS_CLK_PERIOD;
sys_dip <= X"AA"; sys_dip <= X"AA";
wait for PERIOD; wait for SYS_CLK_PERIOD;
sys_color_en <= "100"; sys_color_en <= "100";
wait for 10*PERIOD; wait for 10*SYS_CLK_PERIOD;
sys_color_en <= "000"; sys_color_en <= "000";
-- Wait 100 ns for global reset to finish -- Wait 100 ns for global reset to finish
projects/vga_ctrl/src/vga_ctrl_top.vhd
+2 -2
View File
@@ -233,7 +233,7 @@ inst_vga_backend : entity work.vga_backend
); );
--------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------
rst <= sys_rst_in; rst <= sys_rst_in and stat_vga_rdy;
clk <= sys_clk_in; clk <= sys_clk_in;
scan_rdy <= stat_hready and stat_vready; scan_rdy <= stat_hready and stat_vready;
@@ -264,7 +264,7 @@ cpu_reg_read:
when X"05" => -- 05 when X"05" => -- 05
reg := unsigned(sys_dip); reg := unsigned(sys_dip);
when X"0B" => when X"0B" =>
reg := "000000" & cg_rdy & '0'; reg := "000000" & cg_rdy & stat_vga_rdy;
when others => null; when others => null;
end case; end case;
end if; end if;