diff --git a/projects/vga_ctrl/ghdl/tb_vga_ctrl.make b/projects/vga_ctrl/ghdl/tb_vga_ctrl.make
index 305b0f0..bf1d009 100644
--- a/projects/vga_ctrl/ghdl/tb_vga_ctrl.make
+++ b/projects/vga_ctrl/ghdl/tb_vga_ctrl.make
@@ -9,8 +9,8 @@ include $(LIB_PATH)/CPUs/JCpu/ghdl/jcpu_core.inc
 SRCS += $(VGA_BACKEND_SRCS)
 SRCS += $(FIFO_ASYNC_SRCS)
 SRCS += $(JCPU_CORE_SRCS)
-SRCS += ../src/main_xrom.vhdl
-SRCS += ../src/main_irom.vhdl
+SRCS += ../src/sim/main_sim_xrom.vhdl
+SRCS += ../src/sim/main_sim_irom.vhdl
 SRCS += ../src/cpu_embedded.vhd
 SRCS += ../src/vga_ctrl_top.vhd
 SRCS += ../src/tb_vga_ctrl.vhd
@@ -19,7 +19,7 @@ SRCS += ../src/tb_vga_ctrl.vhd
 # Compile
 TARGET := tb_vga_ctrl
 ENTITY := tb_vga_ctrl
-RUN_TIME := 250us
+RUN_TIME := 2500us
 
 include $(VHDL_HOME)/make/ghdl.mk
 # -----------------------------------------------------------
diff --git a/projects/vga_ctrl/src/tb_vga_ctrl.vhd b/projects/vga_ctrl/src/tb_vga_ctrl.vhd
index 680ad45..52c7701 100644
--- a/projects/vga_ctrl/src/tb_vga_ctrl.vhd
+++ b/projects/vga_ctrl/src/tb_vga_ctrl.vhd
@@ -68,7 +68,10 @@ ARCHITECTURE behavior OF tb_vga_ctrl IS
 	END COMPONENT;
 
 	--Constants
+	constant tsvga			: vga_timespec_t := ts_vga_testbench;
 	constant PERIOD : time := 10 ns;
+	constant SYS_CLK_PERIOD		: time := 10 ns;
+	constant VGA_CLK_PERIOD	: time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns;
 
 	--Inputs
 	SIGNAL sys_rst_in :  std_logic := '1';
@@ -100,7 +103,7 @@ BEGIN
 	uut: vga_ctrl_top 
 	GENERIC MAP 
 	(
-		tsvga		=> ts_vga_testbench
+		tsvga		=> tsvga
 	)
 	PORT MAP
 	(
@@ -123,32 +126,32 @@ BEGIN
 		sys_led => sys_led
 	);
 
- 	tb_clk : PROCESS
+ 	sys_clk : PROCESS
 	BEGIN
 		sys_clk_in <= not sys_clk_in;
-		wait for PERIOD/2;
+		wait for SYS_CLK_PERIOD/2;
 	END PROCESS;
 
  	vga_clk : PROCESS
 	BEGIN
 		sys_vga_clk_in <= not sys_vga_clk_in;
-		wait for PERIOD/2;
+		wait for VGA_CLK_PERIOD/2;
 	END PROCESS;
 
 	tb : PROCESS
 	BEGIN
 
 		-- Wait 100 ns for global reset to finish
-		wait for 100*PERIOD;
+		wait for 100*SYS_CLK_PERIOD;
 		sys_rst_in <= '0';
 
-		wait for PERIOD;
+		wait for SYS_CLK_PERIOD;
 		sys_dip <= X"AA";
 
-		wait for PERIOD;
+		wait for SYS_CLK_PERIOD;
 		sys_color_en <= "100";
 
-		wait for 10*PERIOD;
+		wait for 10*SYS_CLK_PERIOD;
 		sys_color_en <= "000";
 
 		-- Wait 100 ns for global reset to finish
diff --git a/projects/vga_ctrl/src/vga_ctrl_top.vhd b/projects/vga_ctrl/src/vga_ctrl_top.vhd
index 24c1baf..620185c 100644
--- a/projects/vga_ctrl/src/vga_ctrl_top.vhd
+++ b/projects/vga_ctrl/src/vga_ctrl_top.vhd
@@ -233,7 +233,7 @@ inst_vga_backend : entity work.vga_backend
 	);
 
 	---------------------------------------------------------------------------------------------
-	rst             <= sys_rst_in;
+	rst             <= sys_rst_in and stat_vga_rdy;
 	clk				<= sys_clk_in;
 
 	scan_rdy		<= stat_hready and stat_vready;
@@ -264,7 +264,7 @@ cpu_reg_read:
 			when X"05" =>	-- 05 
 				reg := unsigned(sys_dip);
 			when X"0B" =>
-				reg := "000000" & cg_rdy & '0';
+				reg := "000000" & cg_rdy & stat_vga_rdy;
 			when others => null;
 			end case;
 		end if;