- fixed rst

- use main_sim for test bench git-svn-id: http://moon:8086/svn/vhdl/trunk@1576 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-29 14:14:22 +00:00
parent c34cdf77ac
commit c1e96aecba
3 changed files with 16 additions and 13 deletions
@@ -233,7 +233,7 @@ inst_vga_backend : entity work.vga_backend
 	);

 	---------------------------------------------------------------------------------------------
-	rst             <= sys_rst_in;
+	rst             <= sys_rst_in and stat_vga_rdy;
 	clk				<= sys_clk_in;

 	scan_rdy		<= stat_hready and stat_vready;
@@ -264,7 +264,7 @@ cpu_reg_read:
 			when X"05" =>	-- 05 
 				reg := unsigned(sys_dip);
 			when X"0B" =>
-				reg := "000000" & cg_rdy & '0';
+				reg := "000000" & cg_rdy & stat_vga_rdy;
 			when others => null;
 			end case;
 		end if;