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- fixed rst

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- use main_sim for test bench

git-svn-id: http://moon:8086/svn/vhdl/trunk@1576 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 14:14:22 +00:00
parent c34cdf77ac
commit c1e96aecba
3 changed files with 16 additions and 13 deletions
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projects/vga_ctrl/ghdl/tb_vga_ctrl.make
+3 -3
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@@ -9,8 +9,8 @@ include $(LIB_PATH)/CPUs/JCpu/ghdl/jcpu_core.inc
SRCS += $(VGA_BACKEND_SRCS)
SRCS += $(FIFO_ASYNC_SRCS)
SRCS += $(JCPU_CORE_SRCS)
SRCS += ../src/main_xrom.vhdl
SRCS += ../src/main_irom.vhdl
SRCS += ../src/sim/main_sim_xrom.vhdl
SRCS += ../src/sim/main_sim_irom.vhdl
SRCS += ../src/cpu_embedded.vhd
SRCS += ../src/vga_ctrl_top.vhd
SRCS += ../src/tb_vga_ctrl.vhd
@@ -19,7 +19,7 @@ SRCS += ../src/tb_vga_ctrl.vhd
# Compile
TARGET := tb_vga_ctrl
ENTITY := tb_vga_ctrl
RUN_TIME := 250us
RUN_TIME := 2500us
include $(VHDL_HOME)/make/ghdl.mk
# -----------------------------------------------------------