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- debug output is now record

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git-svn-id: http://moon:8086/svn/vhdl/trunk@999 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-18 07:07:27 +00:00
parent ae123fadc7
commit c0bf39885e
5 changed files with 23 additions and 14 deletions
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lib/CPUs/MIPS/src/tb_mips_top.vhd
+5 -6
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@@ -42,7 +42,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
constant SRAM_ADDR_WIDTH : integer := 17; -- bits
constant FLASH_ADDR_WIDTH : integer := 17; -- bits
signal debug : unsigned(1 downto 0);
signal debug : chip_debug_t;
-- Master
signal nmi : STD_LOGIC := '0';
@@ -399,8 +399,9 @@ SRAM_WRITE:
FLASH_READ:
process(rst, flash_cs_n, flash_oe_n, flash_a)
type file_t is file of integer;
file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_timer.flash.bin";
-- file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
-- file load_flash : file_t open read_mode is "test_dcache.flash.bin";
variable instr : integer;
variable index : natural;
variable temp : signed(31 downto 0);
@@ -441,9 +442,7 @@ STIMULUS: process
begin
gpi_0(23 downto 16) <= "00000000";
gpi_0(28 downto 24) <= "00000";
gpi_0(31) <= 'H';
gpi_0 <= X"00000000";
wait for 3*CLK_PERIOD;
wait until rising_edge(clk);
rst <= '0';