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- debug output is now record

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git-svn-id: http://moon:8086/svn/vhdl/trunk@999 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-08-18 07:07:27 +00:00
parent ae123fadc7
commit c0bf39885e
5 changed files with 23 additions and 14 deletions
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lib/CPUs/MIPS/src/core/mips_top.vhd
+3 -3
View File
@@ -38,7 +38,7 @@ entity mips_top is
);
Port
(
debug : out unsigned(1 downto 0);
debug : out chip_debug_t;
eb : in STD_LOGIC;
nmi : in STD_LOGIC;
cpu_clk : in STD_LOGIC;
@@ -189,8 +189,8 @@ architecture rtl of mips_top is
begin
-------------------------------------------------------------------
debug(0) <= imem_err;
debug(1) <= dmem_err;
debug.imem_err <= imem_err;
debug.dmem_err <= dmem_err;
process(CLK_I)
variable reset_delay : unsigned (31 downto 0);
lib/CPUs/MIPS/src/core/mips_types.vhd
+5
View File
@@ -43,6 +43,11 @@ package mips_types is
subtype sa_t is natural range 0 to 63;
subtype func_t is unsigned(5 downto 0);
type chip_debug_t is record
imem_err : std_logic;
dmem_err : std_logic;
end record;
type op_t is
(
op_illegal,