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- uses now new generic DPRAMs

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git-svn-id: http://moon:8086/svn/vhdl/trunk@941 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-02-09 09:17:40 +00:00
parent c4bbe02cdc
commit bf4ba346c0
5 changed files with 18 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/sim/tb_vga_frontend.fdo
+2 -1
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@@ -3,7 +3,8 @@
## ##
vlib work vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd" vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd" vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
+7 -2
View File
@@ -3,7 +3,8 @@
## ##
vlib work vlib work
vcom -explicit -93 "../../misc/utils_pkg.vhd" vcom -explicit -93 "../../misc/utils_pkg.vhd"
vcom -explicit -93 "../../misc/dpram_1w1r.vhd" vcom -explicit -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
vcom -explicit -93 "../../FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../FIFO/src/gray_counter.vhd"
vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../FIFO/src/fifo_async_ctrl.vhd"
@@ -15,6 +16,10 @@ vcom -explicit -93 "../src/vga_types.vhd"
vcom -explicit -93 "../src/char_gen.vhd" vcom -explicit -93 "../src/char_gen.vhd"
vcom -explicit -93 "../src/vga_sync.vhd" vcom -explicit -93 "../src/vga_sync.vhd"
vcom -explicit -93 "../src/vga_timing.vhd" vcom -explicit -93 "../src/vga_timing.vhd"
vcom -explicit -93 "../src/align_types.vhd"
vcom -explicit -93 "../src/shifter.vhd"
vcom -explicit -93 "../src/align.vhd"
vcom -explicit -93 "../src/align_out.vhd"
vcom -explicit -93 "../src/vga_backend.vhd" vcom -explicit -93 "../src/vga_backend.vhd"
vcom -explicit -93 "../src/vga_frontend64.vhd" vcom -explicit -93 "../src/vga_frontend64.vhd"
vcom -explicit -93 "../src/tb_vga_frontend64.vhd" vcom -explicit -93 "../src/tb_vga_frontend64.vhd"
@@ -24,4 +29,4 @@ do {tb_vga_frontend64.wdo}
view structure view structure
view signals view signals
run 20ms run 10ms
lib/VGA_ctrl/src/char_gen.vhd
+3 -3
View File
@@ -214,14 +214,14 @@ begin
DATA => char_rom_data DATA => char_rom_data
); );
inst_ascii_ram: entity work.dpram_1w1r inst_ascii_ram: entity work.dpram_1w1r2c_ro
GENERIC MAP ( GENERIC MAP (
addr_width => A_RAM_ADDR_WIDTH, addr_width => A_RAM_ADDR_WIDTH,
data_width => A_RAM_DATA_WIDTH data_width => A_RAM_DATA_WIDTH
) )
PORT MAP( PORT MAP(
clka => sys_clk, clk_a => sys_clk,
clkb => vga_clk, clk_b => vga_clk,
en_a => '1', en_a => '1',
en_b => '1', en_b => '1',
we_a => a_ram_we, we_a => a_ram_we,
lib/emac/src/emac_rx.vhd
+3 -3
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@@ -444,7 +444,7 @@ inst_cmd_fifo: entity work.fifo_async
data_r => cmd_fifo_dout data_r => cmd_fifo_dout
); );
inst_ram : entity work.dpram_1w1r inst_ram : entity work.dpram_1w1r2c_ro
GENERIC MAP GENERIC MAP
( (
addr_width => RAM_ADDR_WIDTH, addr_width => RAM_ADDR_WIDTH,
@@ -452,8 +452,8 @@ inst_ram : entity work.dpram_1w1r
) )
PORT MAP PORT MAP
( (
clka => mii_rx_clk, clk_a => mii_rx_clk,
clkb => clk, clk_b => clk,
en_a => ram_en_a, en_a => ram_en_a,
en_b => ram_en_b, en_b => ram_en_b,
we_a => ram_we_a, we_a => ram_we_a,
lib/emac/src/emac_tx.vhd
+3 -3
View File
@@ -562,7 +562,7 @@ xfer_state:
end process; end process;
------------------------------------------------------------------ ------------------------------------------------------------------
inst_ram : entity work.dpram_1w1r inst_ram : entity work.dpram_1w1r2c_ro
GENERIC MAP GENERIC MAP
( (
addr_width => RAM_ADDR_WIDTH, addr_width => RAM_ADDR_WIDTH,
@@ -570,8 +570,8 @@ inst_ram : entity work.dpram_1w1r
) )
PORT MAP PORT MAP
( (
clka => clk, clk_a => clk,
clkb => mii_tx_clk, clk_b => mii_tx_clk,
en_a => ram_en_a, en_a => ram_en_a,
en_b => ram_en_b, en_b => ram_en_b,
we_a => ram_we_a, we_a => ram_we_a,