jens
bf4ba346c0
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@941 cc03376c-175c-47c8-b038-4cd826a8556b
752 lines
18 KiB
VHDL
752 lines
18 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use std.textio.all; -- Imports the standard textio package.
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use work.emac_types.all;
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use work.utils_pkg.all;
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ENTITY emac_tx IS
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Generic
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(
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f_sysclk : real := 100.0;
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RAM_SIZE : natural := 2048
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);
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Port
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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din_vld : in STD_LOGIC;
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din : in unsigned(31 downto 0);
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ctrl_in : in tx_ctrl_in_t;
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ctrl_out : out tx_ctrl_out_t;
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mii_tx_clk : in STD_LOGIC;
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mii_tx_en : out STD_LOGIC;
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mii_tx_er : out STD_LOGIC;
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mii_tx : out unsigned(7 downto 0)
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);
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END emac_tx;
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ARCHITECTURE behavior OF emac_tx IS
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constant RAM_ADDR_WIDTH : natural := NextExpBaseTwo(RAM_SIZE);
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subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
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signal cmd_fifo_din : unsigned(2*word_ptr_t'length-1 downto 0);
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signal cmd_fifo_dout : unsigned(2*word_ptr_t'length-1 downto 0);
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signal cmd_fifo_we : std_logic;
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signal cmd_fifo_re : std_logic;
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signal cmd_fifo_empty : std_logic;
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signal cmd_fifo_full : std_logic;
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signal reset_en : std_logic;
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signal fill_base : word_ptr_t;
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signal fill_size : word_ptr_t;
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signal fill_cnt : word_ptr_t;
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signal fill_ptr : word_ptr_t;
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signal fill_pre_rdy : std_logic;
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signal fill_bsy : std_logic;
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signal fill_remain : unsigned(1 downto 0);
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signal fill_set : std_logic;
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signal fill_en : std_logic;
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signal fill_cnt_en : std_logic;
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signal alloc_OK : std_logic;
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signal alloc_req : std_logic;
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signal alloc_ack : std_logic;
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signal alloc_size : word_ptr_t;
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signal alloc_remain : unsigned(1 downto 0);
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signal commit_en : std_logic;
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signal uncommit_en : std_logic;
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signal mem_alloc_en : std_logic;
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signal mem_free_en : std_logic;
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signal nwords_free : word_ptr_t;
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signal mem_free_req : std_logic;
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signal mem_free_ack : unsigned(1 downto 0);
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signal xfer_size : word_ptr_t;
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signal xfer_ptr : word_ptr_t;
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signal xfer_cnt : word_ptr_t;
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signal xfer_set : std_logic;
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signal xfer_en : std_logic;
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signal xfer_cnt_en : std_logic;
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signal xfer_bsy : std_logic;
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signal xfer_free_en : std_logic;
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signal ram_en_a : std_logic;
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signal ram_we_a : std_logic;
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signal ram_addr_a : word_ptr_t;
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signal ram_din_a : unsigned(35 downto 0);
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signal ram_en_b : std_logic;
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signal ram_addr_b : word_ptr_t;
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signal ram_dout_b : unsigned(35 downto 0);
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signal piso32_din : unsigned(31 downto 0);
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signal piso32_din_be : unsigned(3 downto 0);
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signal piso32_din_rdy : std_logic;
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signal piso32_din_vld : std_logic;
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signal piso32_dout : unsigned(7 downto 0);
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signal piso32_dout_vld : std_logic;
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signal piso32_dout_en : std_logic;
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signal piso8_dout_vld : std_logic;
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signal piso8_din_rdy : std_logic;
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signal piso8_din_vld : std_logic;
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signal piso8_dout : unsigned(3 downto 0);
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signal piso8_din : unsigned(7 downto 0);
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signal reset_pipe : unsigned(31 downto 0);
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signal Gbps_en : std_logic;
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signal fcs_gen_en : std_logic;
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signal fcs_inject_en : std_logic;
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signal fcs_rst : std_logic;
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signal fcs_en : unsigned(7 downto 0);
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signal fcs_vld : std_logic;
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signal fcs_din_vld : std_logic;
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signal fcs : unsigned(31 downto 0);
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signal fcs_rev_endian : unsigned(31 downto 0);
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signal mii_fifo_we : std_logic;
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signal mii_fifo_re : std_logic;
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signal mii_fifo_full : std_logic;
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signal mii_fifo_empty : std_logic;
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signal mii_fifo_re_dly : unsigned(23 downto 0);
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signal mii_bsy : std_logic;
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type host_state_t is (host_init, host_idle, host_alloc, host_setup, host_arm, host_fill, host_commit);
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signal host_s, host_sn : host_state_t;
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type xfer_state_t is (xfer_init, xfer_idle, xfer_start, xfer_preamble0, xfer_preamble1, xfer_active, xfer_crc, xfer_stop, xfer_finish);
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signal xfer_s, xfer_sn : xfer_state_t;
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type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
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constant piso_byte_mask_rom : piso_byte_mask_array_t :=
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(
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"1111",
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"1000",
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"1100",
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"1110"
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);
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signal preamble_en : std_logic;
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signal preamble_addr : natural range 0 to 1;
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type preamble_t is array (0 to 1) of unsigned(31 downto 0);
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constant preamble : preamble_t :=
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(
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X"55555555",
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X"555555D5"
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);
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begin
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ctrl_out.pkt_alloc_req <= alloc_req;
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ctrl_out.pkt_done <= cmd_fifo_empty;
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ctrl_out.reset_busy <= reset_en;
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ram_en_a <= din_vld;
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ram_we_a <= fill_bsy;
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ram_din_a(31 downto 0) <= din;
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ram_din_a(35 downto 32) <= piso_byte_mask_rom(to_integer(fill_remain)) when fill_pre_rdy = '1' else "1111";
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ram_addr_a <= fill_ptr;
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piso32_din <= preamble(preamble_addr) when preamble_en = '1' else fcs_rev_endian when fcs_inject_en = '1' else ram_dout_b(31 downto 0);
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piso32_din_be <= "1111" when (preamble_en = '1' or fcs_inject_en = '1') else ram_dout_b(35 downto 32);
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cmd_fifo_we <= commit_en;
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cmd_fifo_re <= uncommit_en;
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cmd_fifo_din <= fill_size & fill_base;
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ram_en_b <= piso32_din_rdy;
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ram_addr_b <= xfer_ptr;
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reset_en <= reset_pipe(reset_pipe'left);
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xfer_cnt_en <= xfer_bsy and piso32_din_rdy;
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fill_cnt_en <= fill_bsy and din_vld;
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mem_free_en <= not mem_free_ack(0) and mem_free_ack(1);
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fcs_rev_endian <= fcs(7 downto 0) & fcs(15 downto 8) & fcs(23 downto 16) & fcs(31 downto 24);
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------------------------------------------------------------------
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reset_gen:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' or ctrl_in.reset = '1' then
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reset_pipe <= (others => '1');
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else
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reset_pipe <= reset_pipe(reset_pipe'left-1 downto 0) & '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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host_state_next:
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process(clk)
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begin
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if rising_edge(clk) then
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if reset_en = '1' then
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host_s <= host_init;
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else
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host_s <= host_sn;
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end if;
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end if;
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end process;
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host_state:
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process(host_s, alloc_OK, fill_bsy, ctrl_in.pkt_commit_en, alloc_req, mem_free_ack)
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begin
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fill_set <= '0';
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fill_en <= '0';
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commit_en <= '0';
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alloc_ack <= '0';
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mem_alloc_en <= '0';
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host_sn <= host_s;
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case host_s is
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when host_init =>
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host_sn <= host_idle;
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when host_idle =>
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if alloc_req = '1' then
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host_sn <= host_alloc;
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end if;
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when host_alloc =>
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if alloc_OK = '1' then
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host_sn <= host_setup;
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else
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host_sn <= host_idle;
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alloc_ack <= '1';
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end if;
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when host_setup =>
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fill_set <= '1';
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host_sn <= host_arm;
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when host_arm =>
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fill_en <= '1';
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alloc_ack <= '1';
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host_sn <= host_fill;
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when host_fill =>
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fill_en <= '1';
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if alloc_req = '1' then
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host_sn <= host_alloc;
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elsif ctrl_in.pkt_commit_en = '1' then
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host_sn <= host_commit;
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end if;
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when host_commit =>
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if mem_free_ack = "00" then
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commit_en <= '1';
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mem_alloc_en <= '1';
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host_sn <= host_idle;
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end if;
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when others =>
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host_sn <= host_idle;
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end case;
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end process;
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------------------------------------------------------------------
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-- Allocation stuff
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------------------------------------------------------------------
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alloc_request_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if reset_en = '1' then
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alloc_req <= '0';
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elsif ctrl_in.pkt_alloc_en = '1' and alloc_req = '0' then
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alloc_req <= '1';
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alloc_remain <= ctrl_in.tx_size(1 downto 0);
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alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
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if ctrl_in.tx_size(1 downto 0) /= "00" then
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alloc_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
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end if;
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ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
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elsif alloc_ack = '1' then
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alloc_req <= '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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host_alloc_armed_register:
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process(clk)
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begin
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if rising_edge(clk) then
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if reset_en = '1' or commit_en = '1' then
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ctrl_out.pkt_armed <= '0';
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elsif alloc_ack = '1' then
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ctrl_out.pkt_armed <= alloc_OK;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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alloc_eval_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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alloc_OK <= '0';
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if alloc_size < nwords_free then
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alloc_OK <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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fill_base_logic:
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process(clk)
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begin
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if rising_edge(clk) then
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if reset_en = '1' then
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fill_base <= (others => '0');
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elsif commit_en = '1' then
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fill_base <= fill_ptr;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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mem_free_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if reset_en = '1' then
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nwords_free <= (others => '1');
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elsif mem_alloc_en = '1' then
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nwords_free <= nwords_free - fill_size;
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elsif mem_free_en = '1' then
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nwords_free <= nwords_free + xfer_size;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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mem_free_mii:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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if reset_en = '1' then
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mem_free_req <= '0';
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elsif mem_free_ack(0) = '0' then
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if xfer_free_en = '1' then
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mem_free_req <= '1';
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end if;
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else
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mem_free_req <= '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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mem_free_host:
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process(clk)
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begin
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if rising_edge(clk) then
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mem_free_ack(1) <= mem_free_ack(0);
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if reset_en = '1' then
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mem_free_ack <= "00";
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elsif mem_free_req = '1' then
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if mem_alloc_en = '0' then
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mem_free_ack(0) <= '1';
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end if;
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else
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mem_free_ack(0) <= '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- Fill stuff
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------------------------------------------------------------------
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fill_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if fill_set = '1' then
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fill_bsy <= '0';
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fill_pre_rdy <= '0';
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fill_cnt <= alloc_size;
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fill_size <= alloc_size;
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fill_remain <= alloc_remain;
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elsif fill_en = '1' then
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fill_bsy <= '1';
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if fill_cnt_en = '1' or fill_bsy = '0' then
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if fill_cnt /= 1 then
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fill_cnt <= fill_cnt - 1;
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else
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fill_pre_rdy <= '1';
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end if;
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if fill_pre_rdy = '1' then
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fill_bsy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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fill_pointer:
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process(clk)
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begin
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if rising_edge(clk) then
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if fill_set = '1' then
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fill_ptr <= fill_base;
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elsif fill_cnt_en = '1' then
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fill_ptr <= fill_ptr + 1;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- Transfer stuff
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------------------------------------------------------------------
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host2xfer_sync_register:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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Gbps_en <= ctrl_in.Gbps_en;
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fcs_gen_en <= ctrl_in.fcs_gen_en;
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end if;
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end process;
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------------------------------------------------------------------
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xfer_counter:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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xfer_bsy <= '0';
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if xfer_set = '1' then
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xfer_cnt <= cmd_fifo_dout(cmd_fifo_dout'left downto word_ptr_t'length);
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xfer_size <= (others => '0');
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elsif xfer_en = '1' then
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xfer_bsy <= '1';
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if xfer_cnt_en = '1' or xfer_bsy = '0' then
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if xfer_cnt /= 0 then
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xfer_cnt <= xfer_cnt - 1;
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xfer_size <= xfer_size + 1;
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else
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xfer_bsy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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xfer_pointer:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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if xfer_set = '1' then
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xfer_ptr <= cmd_fifo_dout(xfer_ptr'left downto 0);
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elsif xfer_en = '1' then
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if xfer_bsy = '0' or xfer_cnt_en = '1' then
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xfer_ptr <= xfer_ptr + 1;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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xfer_state_next:
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process(mii_tx_clk)
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begin
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if rising_edge(mii_tx_clk) then
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if reset_en = '1' then
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xfer_s <= xfer_init;
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else
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xfer_s <= xfer_sn;
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end if;
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end if;
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end process;
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xfer_state:
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process(xfer_s, mii_bsy, cmd_fifo_empty, piso32_din_rdy, piso32_dout_vld, xfer_bsy, fcs_gen_en)
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begin
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piso32_din_vld <= '0';
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preamble_en <= '0';
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preamble_addr <= 0;
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xfer_set <= '0';
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xfer_en <= '0';
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xfer_free_en <= '0';
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fcs_rst <= '0';
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fcs_inject_en <= '0';
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uncommit_en <= '0';
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xfer_sn <= xfer_s;
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case xfer_s is
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when xfer_init =>
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xfer_sn <= xfer_idle;
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when xfer_idle =>
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if cmd_fifo_empty = '0' and mii_bsy = '0' then
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xfer_sn <= xfer_start;
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end if;
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when xfer_start =>
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if cmd_fifo_empty = '0' then
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xfer_sn <= xfer_preamble0;
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end if;
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when xfer_preamble0 =>
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xfer_set <= '1';
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fcs_rst <= '1';
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preamble_addr <= 0;
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preamble_en <= '1';
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piso32_din_vld <= '1';
|
|
if piso32_din_rdy = '1' then
|
|
xfer_sn <= xfer_preamble1;
|
|
end if;
|
|
|
|
when xfer_preamble1 =>
|
|
preamble_addr <= 1;
|
|
preamble_en <= '1';
|
|
piso32_din_vld <= '1';
|
|
if piso32_din_rdy = '1' then
|
|
xfer_sn <= xfer_active;
|
|
xfer_en <= '1';
|
|
end if;
|
|
|
|
when xfer_active =>
|
|
piso32_din_vld <= xfer_bsy;
|
|
xfer_en <= '1';
|
|
if xfer_bsy = '0' then
|
|
xfer_sn <= xfer_stop;
|
|
end if;
|
|
|
|
when xfer_stop =>
|
|
if piso32_dout_vld = '0' then
|
|
xfer_sn <= xfer_finish;
|
|
if fcs_gen_en = '1' then
|
|
xfer_sn <= xfer_crc;
|
|
end if;
|
|
end if;
|
|
|
|
when xfer_crc =>
|
|
fcs_inject_en <= piso32_din_rdy;
|
|
piso32_din_vld <= '1';
|
|
if piso32_din_rdy = '1' then
|
|
xfer_sn <= xfer_finish;
|
|
end if;
|
|
|
|
when xfer_finish =>
|
|
uncommit_en <= '1';
|
|
xfer_free_en <= '1';
|
|
xfer_sn <= xfer_idle;
|
|
|
|
when others =>
|
|
xfer_sn <= xfer_idle;
|
|
end case;
|
|
|
|
end process;
|
|
|
|
------------------------------------------------------------------
|
|
inst_ram : entity work.dpram_1w1r2c_ro
|
|
GENERIC MAP
|
|
(
|
|
addr_width => RAM_ADDR_WIDTH,
|
|
data_width => ram_din_a'length
|
|
)
|
|
PORT MAP
|
|
(
|
|
clk_a => clk,
|
|
clk_b => mii_tx_clk,
|
|
en_a => ram_en_a,
|
|
en_b => ram_en_b,
|
|
we_a => ram_we_a,
|
|
addr_a => ram_addr_a,
|
|
addr_b => ram_addr_b,
|
|
din_a => ram_din_a,
|
|
dout_b => ram_dout_b
|
|
);
|
|
|
|
------------------------------------------------------------------
|
|
-- Instantiate synchronous FIFO
|
|
inst_cmd_fifo: entity work.fifo_async
|
|
GENERIC MAP
|
|
(
|
|
addr_width => NextExpBaseTwo(RAM_SIZE) - 4, -- RAMSIZE(words)/MIN_PACKET_LEN(words)
|
|
data_width => cmd_fifo_din'length,
|
|
do_last_read_update => true
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => reset_en,
|
|
clk_w => clk,
|
|
clk_r => mii_tx_clk,
|
|
we => cmd_fifo_we,
|
|
re => cmd_fifo_re,
|
|
fifo_full => cmd_fifo_full,
|
|
fifo_empty => cmd_fifo_empty,
|
|
fifo_afull => open,
|
|
fifo_aempty => open,
|
|
data_w => cmd_fifo_din,
|
|
data_r => cmd_fifo_dout
|
|
);
|
|
|
|
------------------------------------------------------------------
|
|
inst_piso32 : entity work.piso
|
|
GENERIC MAP
|
|
(
|
|
data_width_in => 32,
|
|
data_width_out => 8,
|
|
msb_first => true
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => reset_en,
|
|
clk => mii_tx_clk,
|
|
din_vld => piso32_din_vld,
|
|
din_rdy => piso32_din_rdy,
|
|
din_be => piso32_din_be,
|
|
din => piso32_din,
|
|
dout_vld => piso32_dout_vld,
|
|
dout_en => piso32_dout_en,
|
|
dout => piso32_dout
|
|
|
|
);
|
|
|
|
piso32_dout_en <= not mii_fifo_full; --'1' when Gbps_en = '1' else piso8_din_rdy;
|
|
|
|
------------------------------------------------------------------
|
|
fcs_enable_gen:
|
|
process(mii_tx_clk)
|
|
begin
|
|
if rising_edge(mii_tx_clk) then
|
|
if fcs_rst = '1' then
|
|
fcs_en <= (others => '0');
|
|
elsif piso32_dout_vld = '1' then
|
|
fcs_en <= fcs_en(fcs_en'left-1 downto 0) & '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
------------------------------------------------------------------
|
|
inst_fcs: entity work.crc32
|
|
GENERIC MAP
|
|
(
|
|
crc32_init => X"00000000"
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => fcs_rst,
|
|
clk => mii_tx_clk,
|
|
din_vld => fcs_din_vld,
|
|
din => piso32_dout,
|
|
crc32_vld => fcs_vld,
|
|
crc32_out => fcs
|
|
|
|
);
|
|
|
|
fcs_din_vld <= fcs_en(fcs_en'left) and piso32_dout_vld and piso32_dout_en;
|
|
|
|
------------------------------------------------------------------
|
|
-- ensures continous MII-data stream and also acts as Inter Frame Gap delay
|
|
mii_fifo_re_dly_gen:
|
|
process(mii_tx_clk)
|
|
begin
|
|
if rising_edge(mii_tx_clk) then
|
|
if mii_fifo_empty = '1' then
|
|
if Gbps_en = '0' then
|
|
mii_fifo_re_dly <= X"000000"; -- 100 mbps
|
|
else
|
|
mii_fifo_re_dly <= X"000FFF"; -- Gigabit
|
|
end if;
|
|
else
|
|
mii_fifo_re_dly <= mii_fifo_re_dly(mii_fifo_re_dly'left-1 downto 0) & not mii_fifo_empty;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
mii_bsy <= mii_fifo_re_dly(mii_fifo_re_dly'left);
|
|
|
|
------------------------------------------------------------------
|
|
-- Instantiate synchronous FIFO
|
|
inst_mii_fifo: entity work.fifo_sync
|
|
GENERIC MAP
|
|
(
|
|
addr_width => 4,
|
|
data_width => piso32_dout'length,
|
|
do_last_read_update => true
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => reset_en,
|
|
clk => mii_tx_clk,
|
|
we => mii_fifo_we,
|
|
re => mii_fifo_re,
|
|
fifo_full => mii_fifo_full,
|
|
fifo_empty => mii_fifo_empty,
|
|
fifo_afull => open,
|
|
fifo_aempty => open,
|
|
data_w => piso32_dout,
|
|
data_r => piso8_din
|
|
);
|
|
|
|
mii_fifo_re <= mii_bsy when Gbps_en = '1' else (piso8_din_rdy and mii_bsy);
|
|
mii_fifo_we <= piso32_dout_vld;
|
|
|
|
------------------------------------------------------------------
|
|
inst_piso8 : entity work.piso
|
|
GENERIC MAP
|
|
(
|
|
data_width_in => 8,
|
|
data_width_out => 4,
|
|
msb_first => false
|
|
)
|
|
PORT MAP
|
|
(
|
|
rst => reset_en,
|
|
clk => mii_tx_clk,
|
|
din_vld => piso8_din_vld,
|
|
din_rdy => piso8_din_rdy,
|
|
din_be => "11",
|
|
din => piso8_din,
|
|
dout_vld => piso8_dout_vld,
|
|
dout_en => '1',
|
|
dout => piso8_dout
|
|
|
|
);
|
|
|
|
piso8_din_vld <= not mii_fifo_empty and mii_bsy;
|
|
|
|
------------------------------------------------------------------
|
|
mii_output_register:
|
|
process(mii_tx_clk)
|
|
begin
|
|
if rising_edge(mii_tx_clk) then
|
|
mii_tx_er <= '0';
|
|
if Gbps_en = '1' then
|
|
mii_tx_en <= piso8_din_vld;
|
|
mii_tx <= piso8_din;
|
|
else
|
|
mii_tx_en <= piso8_dout_vld;
|
|
mii_tx <= "0000" & piso8_dout;
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
------------------------------------------------------------------
|
|
end behavior;
|