From bf4ba346c0e707954b45988e7c3e513b2e43101c Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Sat, 9 Feb 2013 09:17:40 +0000
Subject: [PATCH] - uses now new generic DPRAMs Committed on the Free edition
 of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features
 and support: http://march-hare.com/cvsnt/

git-svn-id: http://moon:8086/svn/vhdl/trunk@941 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/VGA_ctrl/sim/tb_vga_frontend.fdo   | 3 ++-
 lib/VGA_ctrl/sim/tb_vga_frontend64.fdo | 9 +++++++--
 lib/VGA_ctrl/src/char_gen.vhd          | 6 +++---
 lib/emac/src/emac_rx.vhd               | 6 +++---
 lib/emac/src/emac_tx.vhd               | 6 +++---
 5 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
index 151b8dd..3108918 100644
--- a/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend.fdo
@@ -3,7 +3,8 @@
 ##
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
diff --git a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
index 69fd246..ebfc8b6 100644
--- a/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
+++ b/lib/VGA_ctrl/sim/tb_vga_frontend64.fdo
@@ -3,7 +3,8 @@
 ##
 vlib work
 vcom -explicit  -93 "../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../../misc/dpram_1w1r.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../rams/dpram_1w1r2c_ro_sim.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_ctrl_pkg.vhd"
 vcom -explicit  -93 "../../FIFO/src/gray_counter.vhd"
 vcom -explicit  -93 "../../FIFO/src/fifo_async_ctrl.vhd"
@@ -15,6 +16,10 @@ vcom -explicit  -93 "../src/vga_types.vhd"
 vcom -explicit  -93 "../src/char_gen.vhd"
 vcom -explicit  -93 "../src/vga_sync.vhd"
 vcom -explicit  -93 "../src/vga_timing.vhd"
+vcom -explicit  -93 "../src/align_types.vhd"
+vcom -explicit  -93 "../src/shifter.vhd"
+vcom -explicit  -93 "../src/align.vhd"
+vcom -explicit  -93 "../src/align_out.vhd"
 vcom -explicit  -93 "../src/vga_backend.vhd"
 vcom -explicit  -93 "../src/vga_frontend64.vhd"
 vcom -explicit  -93 "../src/tb_vga_frontend64.vhd"
@@ -24,4 +29,4 @@ do {tb_vga_frontend64.wdo}
 view structure
 view signals
 
-run 20ms
+run 10ms
diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd
index 4dd93b1..f0cb6b8 100644
--- a/lib/VGA_ctrl/src/char_gen.vhd
+++ b/lib/VGA_ctrl/src/char_gen.vhd
@@ -214,14 +214,14 @@ begin
 	    DATA        => char_rom_data
     );
 
-	inst_ascii_ram: entity work.dpram_1w1r
+	inst_ascii_ram: entity work.dpram_1w1r2c_ro
 	GENERIC MAP (
 		addr_width	=> A_RAM_ADDR_WIDTH,
 		data_width	=> A_RAM_DATA_WIDTH
 	)
 	PORT MAP(
-		clka		=> sys_clk,
-		clkb		=> vga_clk,
+		clk_a		=> sys_clk,
+		clk_b		=> vga_clk,
 		en_a		=> '1',
 		en_b		=> '1',
 		we_a		=> a_ram_we,
diff --git a/lib/emac/src/emac_rx.vhd b/lib/emac/src/emac_rx.vhd
index 3c1ef2b..0a72063 100644
--- a/lib/emac/src/emac_rx.vhd
+++ b/lib/emac/src/emac_rx.vhd
@@ -444,7 +444,7 @@ inst_cmd_fifo: entity work.fifo_async
 		data_r		=>  cmd_fifo_dout
 	);
 
-inst_ram : entity work.dpram_1w1r
+inst_ram : entity work.dpram_1w1r2c_ro
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -452,8 +452,8 @@ inst_ram : entity work.dpram_1w1r
 	)
 	PORT MAP 
 	(
-		clka		=> mii_rx_clk,
-		clkb		=> clk,
+		clk_a		=> mii_rx_clk,
+		clk_b		=> clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,
diff --git a/lib/emac/src/emac_tx.vhd b/lib/emac/src/emac_tx.vhd
index e397843..7fffe53 100644
--- a/lib/emac/src/emac_tx.vhd
+++ b/lib/emac/src/emac_tx.vhd
@@ -562,7 +562,7 @@ xfer_state:
 	end process;
 
 ------------------------------------------------------------------
-inst_ram : entity work.dpram_1w1r
+inst_ram : entity work.dpram_1w1r2c_ro
 	GENERIC MAP 
 	(
 		addr_width	=> RAM_ADDR_WIDTH,
@@ -570,8 +570,8 @@ inst_ram : entity work.dpram_1w1r
 	)
 	PORT MAP 
 	(
-		clka		=> clk,
-		clkb		=> mii_tx_clk,
+		clk_a		=> clk,
+		clk_b		=> mii_tx_clk,
 		en_a		=> ram_en_a,
 		en_b		=> ram_en_b,
 		we_a		=> ram_we_a,