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- use BL=2

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1267 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2015-05-30 14:00:04 +00:00
parent dabea0e2ab
commit bca2359c65
1 changed files with 1 additions and 1 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+1 -1
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@@ -47,7 +47,7 @@ package sdram_config is
constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
constant ENABLE_PRE_ALL : std_logic := '1';
constant ENABLE_AUTO_PRE : std_logic := '0';
constant LMR_BL_CURR : natural := LMR_BL1;
constant LMR_BL_CURR : natural := LMR_BL2;
-- DDR-SDR TIMING constants ------------------------------------------------------------------
-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh