diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
index 81924d2..bfddbc3 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd
@@ -47,7 +47,7 @@ package sdram_config is
 	constant BIT_PRE_ALL		: positive := 10; -- bit-position in column address for precharge all (see Data Sheet)
 	constant ENABLE_PRE_ALL		: std_logic := '1';
 	constant ENABLE_AUTO_PRE	: std_logic := '0';
-	constant LMR_BL_CURR		: natural := LMR_BL1;
+	constant LMR_BL_CURR		: natural := LMR_BL2;
 
 	-- DDR-SDR TIMING constants ------------------------------------------------------------------
 	-- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh