From bca2359c65464a1c2117bbec4c0b4165ccbb1bf1 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 30 May 2015 14:00:04 +0000 Subject: [PATCH] - use BL=2 git-svn-id: http://moon:8086/svn/vhdl/trunk@1267 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd index 81924d2..bfddbc3 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_config_mt48lc16m16.vhd @@ -47,7 +47,7 @@ package sdram_config is constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) constant ENABLE_PRE_ALL : std_logic := '1'; constant ENABLE_AUTO_PRE : std_logic := '0'; - constant LMR_BL_CURR : natural := LMR_BL1; + constant LMR_BL_CURR : natural := LMR_BL2; -- DDR-SDR TIMING constants ------------------------------------------------------------------ -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh