diff --git a/lib/FIFO/src/fifo_sync.vhd b/lib/FIFO/src/fifo_sync.vhd
index ff3c52c..3820f39 100644
--- a/lib/FIFO/src/fifo_sync.vhd
+++ b/lib/FIFO/src/fifo_sync.vhd
@@ -29,7 +29,8 @@ USE IEEE.NUMERIC_STD.ALL;
 use work.fifo_ctrl_pkg.all;
 
 entity fifo_sync is
-	Generic (
+	Generic 
+	(
 		addr_width			: natural := 4;
 		data_width			: natural := 8;
 		almost_full_thresh	: integer := 12;
@@ -72,7 +73,7 @@ begin
 	fifo_afull	<= almost_full;
 	fifo_aempty	<= almost_empty;
 
-	inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
+inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl
 	GENERIC MAP
 	(
 		addr_width			=> addr_width,
@@ -96,8 +97,9 @@ begin
 
 	);
 
-	inst_dpram_1w1r: entity work.dpram_1w1r
-	GENERIC MAP (
+inst_dpram_1w1r: entity work.dpram_1w1r
+	GENERIC MAP
+	(
 		addr_width	=> addr_width,
 		data_width	=> data_width
 	)
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
index c04af7b..90308ff 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
@@ -160,7 +160,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		DAT_O	<= X"0000_0000";
+		SDAT_I	<= X"0000_0000";
 		ADDR_O	<= X"0000_0008";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -168,7 +168,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		DAT_O	<= X"0000_0000";
+		SDAT_I	<= X"0000_0000";
 		ADDR_O	<= X"0000_0010";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -176,7 +176,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		DAT_O	<= X"0000_0035";
+		SDAT_I	<= X"0000_0035";
 		ADDR_O	<= X"0000_0004";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
@@ -184,7 +184,7 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		DAT_O	<= X"0000_0035";
+		SDAT_I	<= X"0000_0035";
 		ADDR_O	<= X"0000_0020";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';