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- removed multi-source issue (Xilinx systhesis) for struct using in ports where individual elements are driven by different entities

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- turned async. reset into sync. reset

git-svn-id: http://moon:8086/svn/vhdl/trunk@1200 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 10:11:56 +00:00
parent 4cd72abd34
commit b586cba1b0
3 changed files with 67 additions and 80 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+13 -8
View File
@@ -39,6 +39,7 @@ entity sdram_cmd is
rst : in STD_LOGIC; rst : in STD_LOGIC;
clk : in STD_LOGIC; clk : in STD_LOGIC;
enable : in STD_LOGIC; enable : in STD_LOGIC;
tag : in user_tag_t;
col_addr : in col_addr_t; col_addr : in col_addr_t;
mode_word : in mode_word_t; mode_word : in mode_word_t;
cmd : in sdr_cmd_t; cmd : in sdr_cmd_t;
@@ -82,11 +83,12 @@ begin
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
fsm_sdr_state: fsm_sdr_state:
process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr, tag)
begin begin
st_sdr_next <= st_sdr; st_sdr_next <= st_sdr;
phy_ctrl.part.cmd <= COMMAND(SD_NOP); phy_ctrl.part.cmd <= COMMAND(SD_NOP);
phy_ctrl.part.cke <= enable;
phy_ctrl.u_tag <= tag;
cc_load_en <= '0'; cc_load_en <= '0';
cc_preset <= TIMING(cmd); cc_preset <= TIMING(cmd);
burst_load_en <= '0'; burst_load_en <= '0';
@@ -230,25 +232,27 @@ fsm_sdr_state:
end process; end process;
fsm_sdr_state_next: fsm_sdr_state_next:
process (rst, clk) process (clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
st_sdr <= PWR_DOWN; st_sdr <= PWR_DOWN;
elsif rising_edge(clk) then else
st_sdr <= st_sdr_next; st_sdr <= st_sdr_next;
end if; end if;
end if;
end process; end process;
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
cycle_counter: cycle_counter:
process (rst, clk) process (clk)
variable cycle_cnt : natural range 0 to 15; variable cycle_cnt : natural range 0 to 15;
begin begin
if rising_edge(clk) then
cycle_finished <= '0';
if rst = '1' then if rst = '1' then
cycle_cnt := 0; cycle_cnt := 0;
cycle_finished <= '0'; else
elsif rising_edge(clk) then
cycle_finished <= '0';
if cc_load_en = '1' then if cc_load_en = '1' then
cycle_cnt := cc_preset; cycle_cnt := cc_preset;
elsif cycle_cnt /= 0 then elsif cycle_cnt /= 0 then
@@ -257,6 +261,7 @@ cycle_counter:
cycle_finished <= '1'; cycle_finished <= '1';
end if; end if;
end if; end if;
end if;
end process; end process;
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+17 -30
View File
@@ -363,13 +363,15 @@ fsm_ctrl_state:
end process; end process;
fsm_ctrl_state_next: fsm_ctrl_state_next:
process (rst, clk) process (clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
st_ctrl <= RESET; st_ctrl <= RESET;
elsif rising_edge(clk) then else
st_ctrl <= st_ctrl_next; st_ctrl <= st_ctrl_next;
end if; end if;
end if;
end process; end process;
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
@@ -388,15 +390,15 @@ bank_active_register:
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
user_addr_register: user_addr_register:
process (rst, clk) process (clk)
begin begin
if rising_edge(clk) then
if rst = '1' then if rst = '1' then
bank_addr_reg <= (others => '0'); bank_addr_reg <= (others => '0');
row_addr_reg <= (others => '0'); row_addr_reg <= (others => '0');
col_addr_reg <= (others => '0'); col_addr_reg <= (others => '0');
u_tag_reg <= (others => '0'); u_tag_reg <= (others => '0');
elsif rising_edge(clk) then elsif addr_reg_load_en = '1' then
if addr_reg_load_en = '1' then
bank_addr_last <= bank_addr_reg; bank_addr_last <= bank_addr_reg;
row_addr_last <= row_addr_reg; row_addr_last <= row_addr_reg;
col_addr_last <= col_addr_reg; col_addr_last <= col_addr_reg;
@@ -410,55 +412,42 @@ user_addr_register:
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
power_up_counter: power_up_counter:
process (rst, clk) process (clk)
begin begin
if rst = '1' then if rising_edge(clk) then
pwr_up_cnt <= 0;
pwr_up_finished <= '0';
elsif rising_edge(clk) then
pwr_up_finished <= '0'; pwr_up_finished <= '0';
if pwr_up_cnt_rst = '1' then if pwr_up_cnt_rst = '1' then
pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
else elsif pwr_up_cnt /= 0 then
if pwr_up_cnt /= 0 then
pwr_up_cnt <= pwr_up_cnt - 1; pwr_up_cnt <= pwr_up_cnt - 1;
else else
pwr_up_finished <= '1'; pwr_up_finished <= '1';
end if; end if;
end if; end if;
end if;
end process; end process;
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
refresh_counter: refresh_counter:
process (rst, clk) process (clk)
begin begin
if rst = '1' then if rising_edge(clk) then
refresh_cnt <= 0;
refresh_request <= '0';
elsif rising_edge(clk) then
refresh_request <= '0'; refresh_request <= '0';
if refresh_cnt_rst = '1' then if refresh_cnt_rst = '1' then
refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
else elsif refresh_cnt /= 0 then
if refresh_cnt /= 0 then
refresh_cnt <= refresh_cnt - 1; refresh_cnt <= refresh_cnt - 1;
else else
refresh_request <= '1'; refresh_request <= '1';
end if; end if;
end if; end if;
end if;
end process; end process;
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
cycle_counter: cycle_counter:
process (rst, clk) process (clk)
begin begin
if rst = '1' then if rising_edge(clk) then
cycle_cnt <= 0;
cycle_finished <= '0';
elsif rising_edge(clk) then
cycle_finished <= '0'; cycle_finished <= '0';
if cc_load_en = '1' then if cc_load_en = '1' then
cycle_cnt <= cc_preset; cycle_cnt <= cc_preset;
@@ -472,11 +461,9 @@ cycle_counter:
------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------
seq_counter: seq_counter:
process (rst, clk) process (clk)
begin begin
if rst = '1' then if rising_edge(clk) then
seq_cnt <= 0;
elsif rising_edge(clk) then
if seq_rst_en = '1' then if seq_rst_en = '1' then
seq_cnt <= 0; seq_cnt <= 0;
elsif seq_cnt_en = '1' then elsif seq_cnt_en = '1' then
lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
+4 -9
View File
@@ -78,8 +78,6 @@ architecture rtl of sdram_ctrl_top is
signal sd_cmd_we : std_logic; signal sd_cmd_we : std_logic;
signal cke : std_logic; signal cke : std_logic;
-- signal phy_ctrl : phy_ctrl_t;
-- SD command FIFO -- SD command FIFO
constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length;
signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0);
@@ -101,10 +99,6 @@ architecture rtl of sdram_ctrl_top is
begin begin
---------------------------------
phy_ctrl.part.cke <= cke;
phy_ctrl.u_tag <= sd_tag_fifo_out;
--------------------------------- ---------------------------------
sd_cmd_we <= not cmd_fifo_empty; sd_cmd_we <= not cmd_fifo_empty;
cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); cmd_fifo_in <= to_unsigned(sd_cmd_in, 4);
@@ -170,13 +164,14 @@ begin
( (
rst => sdram_rst0, rst => sdram_rst0,
clk => sdram_clk0, clk => sdram_clk0,
phy_ctrl => phy_ctrl,
enable => cke, enable => cke,
tag => sd_tag_fifo_out,
col_addr => sd_col_fifo_out,
mode_word => sd_mode_fifo_out,
cmd => sd_cmd, cmd => sd_cmd,
cmd_we => sd_cmd_we, cmd_we => sd_cmd_we,
cmd_ack => cmd_fifo_re, cmd_ack => cmd_fifo_re,
col_addr => sd_col_fifo_out, phy_ctrl => phy_ctrl
mode_word => sd_mode_fifo_out
); );