diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index d014414..63ee6ad 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -39,6 +39,7 @@ entity sdram_cmd is rst : in STD_LOGIC; clk : in STD_LOGIC; enable : in STD_LOGIC; + tag : in user_tag_t; col_addr : in col_addr_t; mode_word : in mode_word_t; cmd : in sdr_cmd_t; @@ -82,20 +83,21 @@ begin ------------------------------------------------------------------------------------------ fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) + process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr, tag) begin - st_sdr_next <= st_sdr; - phy_ctrl.part.cmd <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BURST_LEN/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; + st_sdr_next <= st_sdr; + phy_ctrl.part.cmd <= COMMAND(SD_NOP); + phy_ctrl.part.cke <= enable; + phy_ctrl.u_tag <= tag; + cc_load_en <= '0'; + cc_preset <= TIMING(cmd); + burst_load_en <= '0'; + cmd_ack <= '0'; + burst_preset <= BURST_LEN/2-1; + phy_ctrl.re <= '0'; + phy_ctrl.drive_en <= '0'; + phy_ctrl.we <= '0'; + phy_ctrl.utag_we <= '0'; phy_ctrl.part.addr <= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right); phy_ctrl.part.ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); @@ -230,32 +232,35 @@ fsm_sdr_state: end process; fsm_sdr_state_next: - process (rst, clk) + process (clk) begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; + if rising_edge(clk) then + if rst = '1' then + st_sdr <= PWR_DOWN; + else + st_sdr <= st_sdr_next; + end if; end if; end process; ------------------------------------------------------------------------------------------ cycle_counter: - process (rst, clk) + process (clk) variable cycle_cnt : natural range 0 to 15; begin - if rst = '1' then - cycle_cnt := 0; + if rising_edge(clk) then cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; + if rst = '1' then + cycle_cnt := 0; else - cycle_finished <= '1'; - end if; + if cc_load_en = '1' then + cycle_cnt := cc_preset; + elsif cycle_cnt /= 0 then + cycle_cnt := cycle_cnt - 1; + else + cycle_finished <= '1'; + end if; + end if; end if; end process; diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd index 0942494..944d0ab 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd @@ -363,12 +363,14 @@ fsm_ctrl_state: end process; fsm_ctrl_state_next: - process (rst, clk) + process (clk) begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; + if rising_edge(clk) then + if rst = '1' then + st_ctrl <= RESET; + else + st_ctrl <= st_ctrl_next; + end if; end if; end process; @@ -388,15 +390,15 @@ bank_active_register: ------------------------------------------------------------------------------------------ user_addr_register: - process (rst, clk) + process (clk) begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then + if rising_edge(clk) then + if rst = '1' then + bank_addr_reg <= (others => '0'); + row_addr_reg <= (others => '0'); + col_addr_reg <= (others => '0'); + u_tag_reg <= (others => '0'); + elsif addr_reg_load_en = '1' then bank_addr_last <= bank_addr_reg; row_addr_last <= row_addr_reg; col_addr_last <= col_addr_reg; @@ -410,21 +412,16 @@ user_addr_register: ------------------------------------------------------------------------------------------ power_up_counter: - process (rst, clk) + process (clk) begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then + if rising_edge(clk) then pwr_up_finished <= '0'; if pwr_up_cnt_rst = '1' then pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; + elsif pwr_up_cnt /= 0 then + pwr_up_cnt <= pwr_up_cnt - 1; else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; + pwr_up_finished <= '1'; end if; end if; end process; @@ -432,33 +429,25 @@ power_up_counter: ------------------------------------------------------------------------------------------ refresh_counter: - process (rst, clk) + process (clk) begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then + if rising_edge(clk) then refresh_request <= '0'; if refresh_cnt_rst = '1' then refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; + elsif refresh_cnt /= 0 then + refresh_cnt <= refresh_cnt - 1; else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; + refresh_request <= '1'; end if; end if; end process; ------------------------------------------------------------------------------------------ cycle_counter: - process (rst, clk) + process (clk) begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then + if rising_edge(clk) then cycle_finished <= '0'; if cc_load_en = '1' then cycle_cnt <= cc_preset; @@ -472,11 +461,9 @@ cycle_counter: ------------------------------------------------------------------------------------------ seq_counter: - process (rst, clk) + process (clk) begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then + if rising_edge(clk) then if seq_rst_en = '1' then seq_cnt <= 0; elsif seq_cnt_en = '1' then diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd index efad6f5..1f39b34 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd @@ -78,8 +78,6 @@ architecture rtl of sdram_ctrl_top is signal sd_cmd_we : std_logic; signal cke : std_logic; --- signal phy_ctrl : phy_ctrl_t; - -- SD command FIFO constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); @@ -101,10 +99,6 @@ architecture rtl of sdram_ctrl_top is begin - --------------------------------- - phy_ctrl.part.cke <= cke; - phy_ctrl.u_tag <= sd_tag_fifo_out; - --------------------------------- sd_cmd_we <= not cmd_fifo_empty; cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); @@ -170,13 +164,14 @@ begin ( rst => sdram_rst0, clk => sdram_clk0, - phy_ctrl => phy_ctrl, enable => cke, + tag => sd_tag_fifo_out, + col_addr => sd_col_fifo_out, + mode_word => sd_mode_fifo_out, cmd => sd_cmd, cmd_we => sd_cmd_we, cmd_ack => cmd_fifo_re, - col_addr => sd_col_fifo_out, - mode_word => sd_mode_fifo_out + phy_ctrl => phy_ctrl );