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- removed multi-source issue (Xilinx systhesis) for struct using in ports where individual elements are driven by different entities

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- turned async. reset into sync. reset

git-svn-id: http://moon:8086/svn/vhdl/trunk@1200 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 10:11:56 +00:00
parent 4cd72abd34
commit b586cba1b0
3 changed files with 67 additions and 80 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
+29 -42
View File
@@ -363,12 +363,14 @@ fsm_ctrl_state:
end process;
fsm_ctrl_state_next:
process (rst, clk)
process (clk)
begin
if rst = '1' then
st_ctrl <= RESET;
elsif rising_edge(clk) then
st_ctrl <= st_ctrl_next;
if rising_edge(clk) then
if rst = '1' then
st_ctrl <= RESET;
else
st_ctrl <= st_ctrl_next;
end if;
end if;
end process;
@@ -388,15 +390,15 @@ bank_active_register:
------------------------------------------------------------------------------------------
user_addr_register:
process (rst, clk)
process (clk)
begin
if rst = '1' then
bank_addr_reg <= (others => '0');
row_addr_reg <= (others => '0');
col_addr_reg <= (others => '0');
u_tag_reg <= (others => '0');
elsif rising_edge(clk) then
if addr_reg_load_en = '1' then
if rising_edge(clk) then
if rst = '1' then
bank_addr_reg <= (others => '0');
row_addr_reg <= (others => '0');
col_addr_reg <= (others => '0');
u_tag_reg <= (others => '0');
elsif addr_reg_load_en = '1' then
bank_addr_last <= bank_addr_reg;
row_addr_last <= row_addr_reg;
col_addr_last <= col_addr_reg;
@@ -410,21 +412,16 @@ user_addr_register:
------------------------------------------------------------------------------------------
power_up_counter:
process (rst, clk)
process (clk)
begin
if rst = '1' then
pwr_up_cnt <= 0;
pwr_up_finished <= '0';
elsif rising_edge(clk) then
if rising_edge(clk) then
pwr_up_finished <= '0';
if pwr_up_cnt_rst = '1' then
pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1;
elsif pwr_up_cnt /= 0 then
pwr_up_cnt <= pwr_up_cnt - 1;
else
if pwr_up_cnt /= 0 then
pwr_up_cnt <= pwr_up_cnt - 1;
else
pwr_up_finished <= '1';
end if;
pwr_up_finished <= '1';
end if;
end if;
end process;
@@ -432,33 +429,25 @@ power_up_counter:
------------------------------------------------------------------------------------------
refresh_counter:
process (rst, clk)
process (clk)
begin
if rst = '1' then
refresh_cnt <= 0;
refresh_request <= '0';
elsif rising_edge(clk) then
if rising_edge(clk) then
refresh_request <= '0';
if refresh_cnt_rst = '1' then
refresh_cnt <= REFRESH_CLOCK_INTERVAL-1;
elsif refresh_cnt /= 0 then
refresh_cnt <= refresh_cnt - 1;
else
if refresh_cnt /= 0 then
refresh_cnt <= refresh_cnt - 1;
else
refresh_request <= '1';
end if;
refresh_request <= '1';
end if;
end if;
end process;
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
process (clk)
begin
if rst = '1' then
cycle_cnt <= 0;
cycle_finished <= '0';
elsif rising_edge(clk) then
if rising_edge(clk) then
cycle_finished <= '0';
if cc_load_en = '1' then
cycle_cnt <= cc_preset;
@@ -472,11 +461,9 @@ cycle_counter:
------------------------------------------------------------------------------------------
seq_counter:
process (rst, clk)
process (clk)
begin
if rst = '1' then
seq_cnt <= 0;
elsif rising_edge(clk) then
if rising_edge(clk) then
if seq_rst_en = '1' then
seq_cnt <= 0;
elsif seq_cnt_en = '1' then