- removed multi-source issue (Xilinx systhesis) for struct using in ports where individual elements are driven by different entities

- turned async. reset into sync. reset

git-svn-id: http://moon:8086/svn/vhdl/trunk@1200 cc03376c-175c-47c8-b038-4cd826a8556b

lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd

@@ -39,6 +39,7 @@ entity sdram_cmd is
 		rst				: in  STD_LOGIC;
 		clk				: in  STD_LOGIC;
 		enable			: in  STD_LOGIC;
+		tag				: in user_tag_t;
 		col_addr		: in col_addr_t;
 		mode_word		: in  mode_word_t;
 		cmd				: in  sdr_cmd_t;
@@ -82,20 +83,21 @@ begin
 ------------------------------------------------------------------------------------------
 
 fsm_sdr_state:
-	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
+	process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr, tag)
 	begin
-		st_sdr_next		<= st_sdr;
-		phy_ctrl.part.cmd <= COMMAND(SD_NOP);
-		
-		cc_load_en <= '0';
-		cc_preset <= TIMING(cmd);
-		burst_load_en <= '0';
-		cmd_ack	<= '0';
-		burst_preset <= BURST_LEN/2-1;
-		phy_ctrl.re <= '0';
-		phy_ctrl.drive_en <= '0';
-		phy_ctrl.we <= '0';
-		phy_ctrl.utag_we <= '0';
+		st_sdr_next			<= st_sdr;
+		phy_ctrl.part.cmd	<= COMMAND(SD_NOP);
+		phy_ctrl.part.cke	<= enable;
+		phy_ctrl.u_tag		<= tag;
+		cc_load_en			<= '0';
+		cc_preset			<= TIMING(cmd);
+		burst_load_en		<= '0';
+		cmd_ack				<= '0';
+		burst_preset		<= BURST_LEN/2-1;
+		phy_ctrl.re			<= '0';
+		phy_ctrl.drive_en	<= '0';
+		phy_ctrl.we			<= '0';
+		phy_ctrl.utag_we	<= '0';
 		phy_ctrl.part.addr	<= mode_word(phy_ctrl.part.addr'left downto phy_ctrl.part.addr'right);
 		phy_ctrl.part.ba	<= mode_word(mode_word_t'left downto mode_word_t'left-1);
 		
@@ -230,32 +232,35 @@ fsm_sdr_state:
 	end process;
 	
 fsm_sdr_state_next:
-	process (rst, clk)
+	process (clk)
 	begin
-		if rst = '1' then
-			st_sdr		<= PWR_DOWN;
-		elsif rising_edge(clk) then
-			st_sdr		<= st_sdr_next;
+		if rising_edge(clk) then
+			if rst = '1' then
+				st_sdr		<= PWR_DOWN;
+			else
+				st_sdr		<= st_sdr_next;
+			end if;
 		end if;
 	end process;
 	
 ------------------------------------------------------------------------------------------
 cycle_counter:
-	process (rst, clk)
+	process (clk)
 	variable cycle_cnt : natural range 0 to 15;
 	begin
-		if rst = '1' then
-			cycle_cnt	:= 0;
+		if rising_edge(clk) then
 			cycle_finished	<= '0';
-		elsif rising_edge(clk) then
-			cycle_finished	<= '0';
-			if cc_load_en = '1' then
-				cycle_cnt := cc_preset;
-			elsif cycle_cnt /= 0 then
-				cycle_cnt := cycle_cnt - 1;
+			if rst = '1' then
+				cycle_cnt	:= 0;
 			else
-				cycle_finished	<= '1';
-			end if;	
+				if cc_load_en = '1' then
+					cycle_cnt := cc_preset;
+				elsif cycle_cnt /= 0 then
+					cycle_cnt := cycle_cnt - 1;
+				else
+					cycle_finished	<= '1';
+				end if;	
+			end if;
 		end if;
 	end process;