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renamed clock entity

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1170 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-23 08:42:51 +00:00
parent c6323411e1
commit b1dfffbc2a
2 changed files with 3 additions and 3 deletions
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lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
+2 -2
View File
@@ -30,7 +30,7 @@ USE WORK.utils_pkg.ALL;
Library UNISIM; Library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
entity clockgen is entity sdram_clk is
generic generic
( (
clk_in_freq : real := 100.0; clk_in_freq : real := 100.0;
@@ -52,7 +52,7 @@ entity clockgen is
); );
end; end;
architecture tech of clockgen is architecture tech of sdram_clk is
signal locked : unsigned(1 downto 0); signal locked : unsigned(1 downto 0);
signal dcm_rst : unsigned(1 downto 0); signal dcm_rst : unsigned(1 downto 0);
lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+1 -1
View File
@@ -101,7 +101,7 @@ begin
rst0_out <= rst0; rst0_out <= rst0;
------------------------------------------------------------------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------------------------------------------------------------------
inst_clockgen : entity work.clockgen inst_sdram_clk : entity work.sdram_clk
GENERIC MAP GENERIC MAP
( (
clk_in_freq => f_sdrclk, clk_in_freq => f_sdrclk,