diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
index 73a4c0e..3e63f3b 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
@@ -30,7 +30,7 @@ USE WORK.utils_pkg.ALL;
 Library UNISIM;
 use UNISIM.vcomponents.all;
 
-entity clockgen is
+entity sdram_clk is
 	generic
 	(
 		clk_in_freq			: real		:= 100.0;
@@ -52,7 +52,7 @@ entity clockgen is
 	);
 end;
 
-architecture tech of clockgen is
+architecture tech of sdram_clk is
 
 	signal locked					: unsigned(1 downto 0);
 	signal dcm_rst					: unsigned(1 downto 0);
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
index ec07fe6..ef9f524 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
@@ -101,7 +101,7 @@ begin
 	rst0_out	<= rst0;
 	
 ------------------------------------------------------------------------------------------------------------------------------------------------
-inst_clockgen : entity work.clockgen
+inst_sdram_clk : entity work.sdram_clk
 	GENERIC MAP
 	(
 		clk_in_freq			=> f_sdrclk,