From b1dfffbc2a5efa1f48a5c0fb7d12992d84d6cabd Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 23 May 2015 08:42:51 +0000 Subject: [PATCH] renamed clock entity git-svn-id: http://moon:8086/svn/vhdl/trunk@1170 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd | 4 ++-- lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd index 73a4c0e..3e63f3b 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd @@ -30,7 +30,7 @@ USE WORK.utils_pkg.ALL; Library UNISIM; use UNISIM.vcomponents.all; -entity clockgen is +entity sdram_clk is generic ( clk_in_freq : real := 100.0; @@ -52,7 +52,7 @@ entity clockgen is ); end; -architecture tech of clockgen is +architecture tech of sdram_clk is signal locked : unsigned(1 downto 0); signal dcm_rst : unsigned(1 downto 0); diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd index ec07fe6..ef9f524 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd @@ -101,7 +101,7 @@ begin rst0_out <= rst0; ------------------------------------------------------------------------------------------------------------------------------------------------ -inst_clockgen : entity work.clockgen +inst_sdram_clk : entity work.sdram_clk GENERIC MAP ( clk_in_freq => f_sdrclk,