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- added timing constraints

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1021 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2013-08-24 16:34:44 +00:00
parent f81cd4018f
commit b12bb21d64
1 changed files with 7 additions and 0 deletions
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lib/CPUs/MIPS/syn/ise101/constraints/mips_top.xcf
+7
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@@ -1,3 +1,10 @@
# Bus clock nets
NET "CLK_I" TNM_NET = "sys_clk";
TIMESPEC "TS_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET "cpu_clk" TNM_NET = "cpu_clk";
TIMESPEC "TS_cpu_clk" = PERIOD "cpu_clk" 9.9 ns HIGH 50 %;
BEGIN MODEL biu
INST inst_bin_fifo ram_style = distributed;
INST inst_bout_fifo ram_style = distributed;