Unified RAM memory content signals

lib/rams/xilinx/src/dpram_1w1r2c_ra.vhd

@@ -48,19 +48,19 @@ end dpram_1w1r2c_ra;
 architecture Behavioral of dpram_1w1r2c_ra is
 
 	constant depth : integer := 2**addr_width;
-	type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0);
-	signal RAM : RAMtype;
+	type memory_type is array (0 to depth-1) of unsigned (data_width-1 downto 0);
+	signal memory_content : memory_type;
 	signal addr_b_r : unsigned (addr_width-1 downto 0);
 	
 begin
 
-	dout_b <= RAM(to_integer(addr_b_r));
+	dout_b <= memory_content(to_integer(addr_b_r));
 
 process (clk_a)
 begin
 if clk_a'event and clk_a = '1' then
 	if we_a = '1' then
-		RAM(to_integer(addr_a)) <= din_a;
+		memory_content(to_integer(addr_a)) <= din_a;
 	end if;
 end if;
 end process;