From ae123fadc74b8eb305aab2e73b43bc4e4021be22 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 10 Aug 2013 17:24:44 +0000 Subject: [PATCH] - change instructionamesfor nop and illegal Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@997 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_instr.vhd | 2 +- lib/CPUs/MIPS/src/core/mips_pipeline.vhd | 12 ++++++------ lib/CPUs/MIPS/src/core/mips_types.vhd | 4 ++-- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd index b187444..cdb6115 100644 --- a/lib/CPUs/MIPS/src/core/mips_instr.vhd +++ b/lib/CPUs/MIPS/src/core/mips_instr.vhd @@ -157,7 +157,7 @@ package body mips_instr is rt := to_integer(extract_rt(instr)); rs := to_integer(extract_rs(instr)); - result := reserved; + result := op_illegal; case opc is diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd index 0dc3689..38dd440 100644 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd @@ -485,7 +485,7 @@ proc_stage_ID_EX_1: begin if rising_edge(clk_1) then if stage_rst(1) = '1' then - EX_stage.op <= NOP; + EX_stage.op <= op_nop; EX_stage.IR <= (others => '0'); EX_stage.ctrl <= ctrl_lines_default; EX_stage.reg_write <= '0'; @@ -504,7 +504,7 @@ proc_stage_ID_EX_1: EX_stage.pcn <= ID_stage.pcn; EX_stage.epc <= ID_stage.epc; if sdu.EX_nop = '1' then - EX_stage.op <= NOP; + EX_stage.op <= op_nop; EX_stage.IR <= (others => '0'); EX_stage.ctrl <= ctrl_lines_default; EX_stage.reg_write <= '0'; @@ -744,7 +744,7 @@ proc_stage_MEM_n: begin if rising_edge(clk_1) then if stage_rst(2) = '1' then - MEM_stage.op <= NOP; + MEM_stage.op <= op_nop; MEM_stage.wreg_we <= '0'; MEM_stage.ctrl <= ctrl_lines_default; MEM_stage.pa_off <= (others => '0'); @@ -775,7 +775,7 @@ proc_stage_MEM_n: MEM_stage.ex_result <= EX_stage.result; end if; if sdu.MEM_nop = '1' then - MEM_stage.op <= NOP; + MEM_stage.op <= op_nop; MEM_stage.wreg_we <= '0'; MEM_stage.ctrl <= ctrl_lines_default; else @@ -835,7 +835,7 @@ proc_stage_WB_p: begin if rising_edge(clk_1) then if stage_rst(3) = '1' then - WB_stage.op <= NOP; + WB_stage.op <= op_nop; WB_stage.wreg_we <= '1'; WB_stage.reg_wptr <= (others => '0'); WB_stage.data <= (others => '0'); @@ -854,7 +854,7 @@ proc_stage_WB_p: end if; WB_stage.nop <= sdu.WB_nop; if sdu.WB_nop = '1' then - WB_stage.op <= NOP; + WB_stage.op <= op_nop; WB_stage.wreg_we <= '0'; else WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd index 6cf2bad..6ad9662 100644 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ b/lib/CPUs/MIPS/src/core/mips_types.vhd @@ -45,8 +45,8 @@ package mips_types is type op_t is ( - reserved, - nop, + op_illegal, + op_nop, op_sll, op_srl, op_sra,