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git-svn-id: http://moon:8086/svn/vhdl/trunk@1193 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-05-24 09:10:18 +00:00
parent 75583b4cc4
commit a4395aba8a
3 changed files with 91 additions and 99 deletions
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lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo
+5 -5
View File
@@ -18,13 +18,13 @@ vcom -explicit -93 "../src/sdram_ctrl.vhd"
vcom -explicit -93 "../src/ddr_clk_virtex4.vhd"
vcom -explicit -93 "../src/ddr_phy_virtex4.vhd"
vcom -explicit -93 "../src/sdram_ctrl_top.vhd"
vcom -explicit -93 "../src/sdram_ctrl_frontend_wb.vhd"
vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd"
vcom -explicit -93 "../src/ctrl_ddr_wb64.vhd"
vcom -explicit -93 "../src/mt46v16m16.vhd"
vcom -explicit -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
vcom -explicit -93 "../src/tb_ctrl_ddr_wb64.vhd"
#restart -force
vsim -t 1ps -lib work tb_sdram_ctrl_frontend_wb
do {tb_sdram_ctrl_frontend_wb.wdo}
vsim -t 1ps -lib work tb_ctrl_ddr_wb64
do {tb_ctrl_ddr_wb64.wdo}
view wave
view structure
view signals
lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo
+37 -45
View File
@@ -1,50 +1,42 @@
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
add wave -noupdate -divider DEBUG
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_din
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_dout
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_re
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_we
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_full
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_empty
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk_fb
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk0
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_rst0
add wave -noupdate -divider Part
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg
add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
add wave -noupdate -divider J-Bus
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/clk_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/rst_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/cyc_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/stb_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/we_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sel_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/ack_i
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/mrdy_o
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/srdy_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/addr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_o
add wave -noupdate -divider SDRAM
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk_fb
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_p
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_n
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cke
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cs_n
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_we_n
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_ras_n
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cas_n
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_ba
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dm
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dqs
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_addr
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_data
add wave -noupdate -divider Test
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sd_cmd
add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/dout_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sddat
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sdsel
add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dout_reg
add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/dout_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
WaveRestoreCursors {{Cursor 1} {189465865 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
@@ -58,4 +50,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {199427964 ps} {200030108 ps}
WaveRestoreZoom {0 ps} {210 us}
lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
+7 -7
View File
@@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL;
use work.sdram_config.all;
use work.sdram_types.all;
entity tb_sdram_ctrl_frontend64_wb is
entity tb_ctrl_ddr_wb64 is
end;
architecture struct of tb_sdram_ctrl_frontend64_wb is
architecture struct of tb_ctrl_ddr_wb64 is
constant CLK_PERIOD : time := 10 ns;
constant SDCLK_PERIOD : time := 7.5 ns;
@@ -115,13 +115,13 @@ begin
SEL_O <= "0000" & sdsel;
-- DDR SDRAM Controller Core
sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
uut : entity work.ctrl_ddr_wb64
GENERIC MAP
(
BL => BURST_LEN,
f_sysclk => 100.000,
f_sdrclk => 133.333,
fifo_depth => 4
BURST_LEN => BURST_LEN,
F_SYSCLK => 100.000,
F_SDRCLK => 133.333,
FIFO_DEPTH => 4
)
PORT MAP
(