diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo
index eeec970..6d94d2b 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.fdo
@@ -1,31 +1,31 @@
-## NOTE:  Do not edit this file.
-##
-if {[file exists work]} {vdel -lib work -all}
-
-vlib work
-vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
-vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
-vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
-vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
-vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
-vcom -explicit  -93 "../src/sdram_config.vhd"
-vcom -explicit  -93 "../src/sdram_types.vhd"
-vcom -explicit  -93 "../src/sdram_cmd.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl.vhd"
-vcom -explicit  -93 "../src/ddr_clk_virtex4.vhd"
-vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
-vcom -explicit  -93 "../src/sdram_ctrl_frontend_wb.vhd"
-vcom -explicit  -93 "../src/mt46v16m16.vhd"
-vcom -explicit  -93 "../src/tb_sdram_ctrl_frontend_wb.vhd"
-
-#restart -force
-vsim -t 1ps   -lib work tb_sdram_ctrl_frontend_wb
-do {tb_sdram_ctrl_frontend_wb.wdo}
-view wave
-view structure
-view signals
-run 200us
+## NOTE:  Do not edit this file.
+##
+if {[file exists work]} {vdel -lib work -all}
+
+vlib work
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../src/sdram_config.vhd"
+vcom -explicit  -93 "../src/sdram_types.vhd"
+vcom -explicit  -93 "../src/sdram_cmd.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl.vhd"
+vcom -explicit  -93 "../src/ddr_clk_virtex4.vhd"
+vcom -explicit  -93 "../src/ddr_phy_virtex4.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_top.vhd"
+vcom -explicit  -93 "../src/sdram_ctrl_frontend64_wb.vhd"
+vcom -explicit  -93 "../src/ctrl_ddr_wb64.vhd"
+vcom -explicit  -93 "../src/mt46v16m16.vhd"
+vcom -explicit  -93 "../src/tb_ctrl_ddr_wb64.vhd"
+
+vsim -t 1ps   -lib work tb_ctrl_ddr_wb64
+do {tb_ctrl_ddr_wb64.wdo}
+view wave
+view structure
+view signals
+run 200us
diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo
index 96f2000..a05c2f0 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo
+++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb64.wdo
@@ -1,61 +1,53 @@
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/clk_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/rst_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/cyc_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/stb_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/we_o
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sel_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/ack_i
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/mrdy_o
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/srdy_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/addr_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_i
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dat_o
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/dout_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/dout_cnt
-add wave -noupdate -divider DEBUG
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_din
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_dout
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_re
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_we
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_full
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/cmd_fifo_empty
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk_fb
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_clk0
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/sdram_rst0
-add wave -noupdate -divider Part
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cs_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_we_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_ras_n
-add wave -noupdate -format Logic /tb_sdram_ctrl_frontend_wb/part_cas_n
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_ba
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dm
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/part_dqs
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/part_data
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr
-add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend_wb/sdram_ctrl_frontend_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg
-add wave -noupdate -format Literal /tb_sdram_ctrl_frontend_wb/sd_cmd
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {199582900 ps} 0}
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-update
-WaveRestoreZoom {199427964 ps} {200030108 ps}
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider J-Bus
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/clk_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/rst_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/cyc_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/stb_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/we_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sel_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/ack_i
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/mrdy_o
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dat_o
+add wave -noupdate -divider SDRAM
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/sdclk_fb
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_p
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_clk_n
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cke
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cs_n
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_we_n
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_ras_n
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/part_cas_n
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_ba
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dm
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/part_dqs
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/part_data
+add wave -noupdate -divider Test
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sd_cmd
+add wave -noupdate -format Logic /tb_ctrl_ddr_wb64/dout_rst
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/sddat
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/sdsel
+add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb64/dout_reg
+add wave -noupdate -format Literal /tb_ctrl_ddr_wb64/dout_cnt
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {189465865 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {210 us}
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
index f8efc0c..fc77bca 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
@@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL;
 use work.sdram_config.all;
 use work.sdram_types.all;
 
-entity tb_sdram_ctrl_frontend64_wb is
+entity tb_ctrl_ddr_wb64 is
 end;
 
-architecture struct of tb_sdram_ctrl_frontend64_wb is
+architecture struct of tb_ctrl_ddr_wb64 is
 
 	constant CLK_PERIOD		: time := 10 ns;
 	constant SDCLK_PERIOD	: time := 7.5 ns;
@@ -115,13 +115,13 @@ begin
 	SEL_O	<= "0000" & sdsel;
 	
 	-- DDR SDRAM Controller Core
-	sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
+	uut : entity work.ctrl_ddr_wb64
 	GENERIC MAP
 	(
-		BL 				=> BURST_LEN,
-		f_sysclk	 	=> 100.000,
-		f_sdrclk	 	=> 133.333,
-		fifo_depth		=> 4
+		BURST_LEN		=> BURST_LEN,
+		F_SYSCLK	 	=> 100.000,
+		F_SDRCLK	 	=> 133.333,
+		FIFO_DEPTH		=> 4
 	)
 	PORT MAP
 	(