- fixed

git-svn-id: http://moon:8086/svn/vhdl/trunk@1193 cc03376c-175c-47c8-b038-4cd826a8556b

lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd

@@ -28,10 +28,10 @@ use IEEE.numeric_std.ALL;
 use work.sdram_config.all;
 use work.sdram_types.all;
 
-entity tb_sdram_ctrl_frontend64_wb is
+entity tb_ctrl_ddr_wb64 is
 end;
 
-architecture struct of tb_sdram_ctrl_frontend64_wb is
+architecture struct of tb_ctrl_ddr_wb64 is
 
 	constant CLK_PERIOD		: time := 10 ns;
 	constant SDCLK_PERIOD	: time := 7.5 ns;
@@ -115,13 +115,13 @@ begin
 	SEL_O	<= "0000" & sdsel;
 	
 	-- DDR SDRAM Controller Core
-	sdram_ctrl_frontend64_wb : entity work.sdram_ctrl_frontend64_wb
+	uut : entity work.ctrl_ddr_wb64
 	GENERIC MAP
 	(
-		BL 				=> BURST_LEN,
-		f_sysclk	 	=> 100.000,
-		f_sdrclk	 	=> 133.333,
-		fifo_depth		=> 4
+		BURST_LEN		=> BURST_LEN,
+		F_SYSCLK	 	=> 100.000,
+		F_SDRCLK	 	=> 133.333,
+		FIFO_DEPTH		=> 4
 	)
 	PORT MAP
 	(