- fixed uart sim

git-svn-id: http://moon:8086/svn/vhdl/trunk@1371 cc03376c-175c-47c8-b038-4cd826a8556b
2017-01-18 22:25:53 +00:00
parent 087210ce5c
commit 9e5fa1c972
2 changed files with 6 additions and 2 deletions
@@ -9,6 +9,10 @@ use std.textio.all; --  Imports the standard textio package.

 ------------------------------------------------------------------------------------
 ENTITY uart IS
+	Generic 
+	(
+		fifo_depth_bits	: integer := 4
+	);
 	Port
 	(
 		clk			: in  STD_LOGIC;