jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- register set extended for future extensions

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@691 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-11-29 16:47:56 +00:00
parent ebf615967c
commit 9a3aa287fd
2 changed files with 129 additions and 86 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+31 -13
View File
@@ -351,7 +351,7 @@ STIMULUS: process
wait for 60000*CLK_PERIOD;
for i in 0 to 3 loop
for i in 0 to 99 loop
-- BLIT test
-- Read status
@@ -363,7 +363,7 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set src addr
-- set src addr first
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
@@ -372,22 +372,40 @@ STIMULUS: process
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src addr last
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000" + to_unsigned(4*(80*4-1), 32);
ADDR_O <= X"0000_0024";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0140";
ADDR_O <= X"0000_002C";
SDAT_O <= to_unsigned(4*80, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr
-- set dst addr first
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0028";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst addr last
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000" + to_unsigned(4*(80*4-1), 32);
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
@@ -395,8 +413,8 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0140";
ADDR_O <= X"0000_0034";
SDAT_O <= to_unsigned(4*80, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
@@ -404,8 +422,8 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_12BF";
ADDR_O <= X"0000_0038";
SDAT_O <= to_unsigned(80-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
@@ -413,8 +431,8 @@ STIMULUS: process
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0000";
ADDR_O <= X"0000_003C";
SDAT_O <= X"0000_0003";
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
@@ -429,7 +447,7 @@ STIMULUS: process
CYC_O <= '0';
WE_O <= '0';
wait for 600000*CLK_PERIOD;
wait for 100000*CLK_PERIOD;
end loop;