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- fixed timing issues

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1589 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 19:11:21 +00:00
parent 47c9f86bae
commit 99a3711411
3 changed files with 71 additions and 65 deletions
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projects/vga_ctrl/src/vga_ctrl_sys.vhd
+4
View File
@@ -71,6 +71,10 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS
SIGNAL vga_ce : std_logic;
constant vga_freq_MHz : real := real(tsvga.f_pxl_clk)/1.0E6;
attribute KEEP : string;
attribute KEEP of vga_clk : signal is "TRUE";
attribute KEEP of vga_rst : signal is "TRUE";
BEGIN
sys_rst <= not sys_rst_n_in;
projects/vga_ctrl/src/vga_ctrl_top.vhd
+7 -6
View File
@@ -92,7 +92,6 @@ architecture Behavioral of vga_ctrl_top is
signal cg_ascii_we : std_logic;
signal cg_posy_we : std_logic;
signal cg_posx_we : std_logic;
signal cg_color : color_t;
signal cg_csr_pos_x : natural range 0 to 80-1;
signal cg_csr_pos_y : natural range 0 to 32-1;
@@ -115,6 +114,7 @@ architecture Behavioral of vga_ctrl_top is
signal cpu_blue : dmem_data_t;
signal cpu_color : color_t;
signal proc_color : color_t;
constant bg_color : color_t := (X"FF", X"FF", X"FF", X"FF"); -- white opaque;
begin
@@ -166,7 +166,7 @@ inst_vga_backend : entity work.vga_backend
color_en(0) <= '1';
color_en(1) <= cg_draw;
color_in(0) <= cpu_color;
color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque
color_in(1) <= bg_color;
color_op <= op_over;
inst_char_gen : entity work.char_gen
@@ -251,7 +251,7 @@ led_out: process (clk)
---------------------------------------------------------------------------------------------
cpu_reg_read:
process(clk, cpu_io_sel, cpu_xrom_data)
process(clk)
variable reg : dmem_data_t;
begin
@@ -278,9 +278,10 @@ cpu_reg_read:
------------------------------------------------------------------
cpu_reg_write:
process(rst, clk)
process(clk)
variable addr : unsigned(dmem_addr_t'length-1 downto 0);
begin
if rising_edge(clk) then
if (rst = '1') then
cpu_led <= (others => '0');
cg_din <= (others => '0');
@@ -292,8 +293,7 @@ cpu_reg_write:
cpu_red <= X"80";
cpu_green <= X"80";
cpu_blue <= X"80";
elsif rising_edge(clk) then
else
cg_posy_we <= '0';
cg_posx_we <= '0';
cg_ascii_we <= '0';
@@ -328,6 +328,7 @@ cpu_reg_write:
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------
projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf
+6 -5
View File
@@ -20,12 +20,12 @@
CONFIG STEPPING = "ES";
# Bus clock nets
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
NET sys_clk_in TNM_NET = "sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET sys_vga_clk TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG;
NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
@@ -33,6 +33,7 @@ NET sys_rst_n_in LOC = D6;
NET sys_rst_n_in PULLUP;
NET sys_rst_n_in TIG;
NET sys_rst_n_in IOSTANDARD = LVCMOS33;
NET vga_rst TIG;
////////////////////////////////////////////////////////////////////////////