From 99a3711411fd9712d69c8359dbf268c27d801279 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Mon, 29 Mar 2021 19:11:21 +0000 Subject: [PATCH] - fixed timing issues git-svn-id: http://moon:8086/svn/vhdl/trunk@1589 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/vga_ctrl/src/vga_ctrl_sys.vhd | 4 + projects/vga_ctrl/src/vga_ctrl_top.vhd | 121 +++++++++--------- .../vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf | 11 +- 3 files changed, 71 insertions(+), 65 deletions(-) diff --git a/projects/vga_ctrl/src/vga_ctrl_sys.vhd b/projects/vga_ctrl/src/vga_ctrl_sys.vhd index 38a9780..474be4a 100644 --- a/projects/vga_ctrl/src/vga_ctrl_sys.vhd +++ b/projects/vga_ctrl/src/vga_ctrl_sys.vhd @@ -71,6 +71,10 @@ ARCHITECTURE behavior OF vga_ctrl_sys IS SIGNAL vga_ce : std_logic; constant vga_freq_MHz : real := real(tsvga.f_pxl_clk)/1.0E6; + attribute KEEP : string; + attribute KEEP of vga_clk : signal is "TRUE"; + attribute KEEP of vga_rst : signal is "TRUE"; + BEGIN sys_rst <= not sys_rst_n_in; diff --git a/projects/vga_ctrl/src/vga_ctrl_top.vhd b/projects/vga_ctrl/src/vga_ctrl_top.vhd index 235f439..efd450b 100644 --- a/projects/vga_ctrl/src/vga_ctrl_top.vhd +++ b/projects/vga_ctrl/src/vga_ctrl_top.vhd @@ -92,7 +92,6 @@ architecture Behavioral of vga_ctrl_top is signal cg_ascii_we : std_logic; signal cg_posy_we : std_logic; signal cg_posx_we : std_logic; - signal cg_color : color_t; signal cg_csr_pos_x : natural range 0 to 80-1; signal cg_csr_pos_y : natural range 0 to 32-1; @@ -115,13 +114,14 @@ architecture Behavioral of vga_ctrl_top is signal cpu_blue : dmem_data_t; signal cpu_color : color_t; signal proc_color : color_t; + constant bg_color : color_t := (X"FF", X"FF", X"FF", X"FF"); -- white opaque; begin inst_vga_backend : entity work.vga_backend GENERIC MAP ( - tsvga => tsvga + tsvga => tsvga ) PORT MAP ( @@ -166,7 +166,7 @@ inst_vga_backend : entity work.vga_backend color_en(0) <= '1'; color_en(1) <= cg_draw; color_in(0) <= cpu_color; - color_in(1) <= cg_color; --(X"FF", X"FF", X"FF", X"FF"); -- white opaque + color_in(1) <= bg_color; color_op <= op_over; inst_char_gen : entity work.char_gen @@ -209,17 +209,17 @@ inst_vga_backend : entity work.vga_backend inst_cpu_embedded: entity work.cpu_embedded PORT MAP ( - rst => cpu_rst, - clk => clk, - ce => cpu_ce, - int_in => cpu_int_in, - int_ack => cpu_int_ack, - xmem_we => cpu_we, - xmem_re => cpu_re, - xmem_din => cpu_din, - xmem_dout => cpu_dout, - xmem_addr => cpu_addr, - io_sel => cpu_io_sel + rst => cpu_rst, + clk => clk, + ce => cpu_ce, + int_in => cpu_int_in, + int_ack => cpu_int_ack, + xmem_we => cpu_we, + xmem_re => cpu_re, + xmem_din => cpu_din, + xmem_dout => cpu_dout, + xmem_addr => cpu_addr, + io_sel => cpu_io_sel ); inst_xrom: entity work.xrom @@ -251,7 +251,7 @@ led_out: process (clk) --------------------------------------------------------------------------------------------- cpu_reg_read: - process(clk, cpu_io_sel, cpu_xrom_data) + process(clk) variable reg : dmem_data_t; begin @@ -278,53 +278,54 @@ cpu_reg_read: ------------------------------------------------------------------ cpu_reg_write: - process(rst, clk) + process(clk) variable addr : unsigned(dmem_addr_t'length-1 downto 0); begin - if (rst = '1') then - cpu_led <= (others => '0'); - cg_din <= (others => '0'); - cg_posy_we <= '0'; - cg_posx_we <= '0'; - cg_ascii_we <= '0'; - cg_clr_line <= '0'; - cg_clr_screen <= '0'; - cpu_red <= X"80"; - cpu_green <= X"80"; - cpu_blue <= X"80"; - - elsif rising_edge(clk) then - cg_posy_we <= '0'; - cg_posx_we <= '0'; - cg_ascii_we <= '0'; - cg_clr_line <= '0'; - cg_clr_screen <= '0'; - addr := cpu_addr; - if cpu_we = '1' then - if cpu_io_sel = '1' then - case addr is - when X"01" => -- 01 - cpu_led <= cpu_dout; - when X"02" => -- 04 - cpu_red <= cpu_dout; - when X"03" => -- 04 - cpu_green <= cpu_dout; - when X"04" => -- 04 - cpu_blue <= cpu_dout; - when X"08" => -- 08 - cg_din <= cpu_dout; - cg_posx_we <= '1'; - when X"09" => -- 09 - cg_din <= cpu_dout; - cg_posy_we <= '1'; - when X"0A" => -- 0A - cg_din <= cpu_dout; - cg_ascii_we <= '1'; - when X"0B" => -- 0B - cg_clr_screen <= cpu_dout(0); - cg_clr_line <= cpu_dout(1); - when others => null; - end case; + if rising_edge(clk) then + if (rst = '1') then + cpu_led <= (others => '0'); + cg_din <= (others => '0'); + cg_posy_we <= '0'; + cg_posx_we <= '0'; + cg_ascii_we <= '0'; + cg_clr_line <= '0'; + cg_clr_screen <= '0'; + cpu_red <= X"80"; + cpu_green <= X"80"; + cpu_blue <= X"80"; + else + cg_posy_we <= '0'; + cg_posx_we <= '0'; + cg_ascii_we <= '0'; + cg_clr_line <= '0'; + cg_clr_screen <= '0'; + addr := cpu_addr; + if cpu_we = '1' then + if cpu_io_sel = '1' then + case addr is + when X"01" => -- 01 + cpu_led <= cpu_dout; + when X"02" => -- 04 + cpu_red <= cpu_dout; + when X"03" => -- 04 + cpu_green <= cpu_dout; + when X"04" => -- 04 + cpu_blue <= cpu_dout; + when X"08" => -- 08 + cg_din <= cpu_dout; + cg_posx_we <= '1'; + when X"09" => -- 09 + cg_din <= cpu_dout; + cg_posy_we <= '1'; + when X"0A" => -- 0A + cg_din <= cpu_dout; + cg_ascii_we <= '1'; + when X"0B" => -- 0B + cg_clr_screen <= cpu_dout(0); + cg_clr_line <= cpu_dout(1); + when others => null; + end case; + end if; end if; end if; end if; diff --git a/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf b/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf index 8624144..4e283f3 100644 --- a/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf +++ b/projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf @@ -20,12 +20,12 @@ CONFIG STEPPING = "ES"; # Bus clock nets -NET sys_clk_in TNM_NET = "sys_clk_in"; -TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %; +NET sys_clk_in TNM_NET = "sys_clk"; +TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %; -NET sys_vga_clk TNM_NET = "vga_clk"; -#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; -TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG; +NET "vga_clk" TNM_NET = "vga_clk"; +TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %; +TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG; NET sys_clk_in LOC = AE14; NET sys_clk_in IOSTANDARD = LVCMOS33; @@ -33,6 +33,7 @@ NET sys_rst_n_in LOC = D6; NET sys_rst_n_in PULLUP; NET sys_rst_n_in TIG; NET sys_rst_n_in IOSTANDARD = LVCMOS33; +NET vga_rst TIG; ////////////////////////////////////////////////////////////////////////////