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- fixed timing issues

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1589 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-29 19:11:21 +00:00
parent 47c9f86bae
commit 99a3711411
3 changed files with 71 additions and 65 deletions
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projects/vga_ctrl/syn/ise/project/vga_ctrl_sys.ucf
+6 -5
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@@ -20,12 +20,12 @@
CONFIG STEPPING = "ES";
# Bus clock nets
NET sys_clk_in TNM_NET = "sys_clk_in";
TIMESPEC "TS_sys_clk_in" = PERIOD "sys_clk_in" 9.9 ns HIGH 50 %;
NET sys_clk_in TNM_NET = "sys_clk";
TIMESPEC "TS_sys_clk" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
NET sys_vga_clk TNM_NET = "vga_clk";
#TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC TS_unrelate = FROM sys_clk_in TO vga_clk TIG;
NET "vga_clk" TNM_NET = "vga_clk";
TIMESPEC "TS_vga_clk" = PERIOD "vga_clk" 7.5 ns HIGH 50 %;
TIMESPEC "TS_unrelate_VGA" = FROM sys_clk TO vga_clk TIG;
NET sys_clk_in LOC = AE14;
NET sys_clk_in IOSTANDARD = LVCMOS33;
@@ -33,6 +33,7 @@ NET sys_rst_n_in LOC = D6;
NET sys_rst_n_in PULLUP;
NET sys_rst_n_in TIG;
NET sys_rst_n_in IOSTANDARD = LVCMOS33;
NET vga_rst TIG;
////////////////////////////////////////////////////////////////////////////