diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd
index 8d63030..41232c6 100644
--- a/lib/CPUs/MIPS/src/core/mips_cop.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_cop.vhd
@@ -79,6 +79,8 @@ architecture Behavioral of cop is
 	signal dcache_info		: unsigned(7 downto 0);
 	signal reg_rptr			: reg_ptr_t;
 	signal reg_wptr			: reg_ptr_t;
+	signal inject_exc		: STD_LOGIC;
+	signal inject_rst		: STD_LOGIC;
 	
 	type cop_pipe_t is record
 		opc			: opcode_t;
@@ -128,7 +130,7 @@ begin
 	cop_pipe_ID.RFE					<= cop_pipe_ID.cs when (cop_pipe_ID.CO = '1' and cop_pipe_ID.func = "010000") else '0';
 	ctrl_out.EB						<= EB_reg xor (status(25) and status(1));
 	ctrl_out.user_mode				<= status(1);
-	
+	ctrl_out.exc_inject				<= inject_exc or inject_rst;
 	cop_pipe_ID.reg_ptr				<= cop_pipe_ID.rd when cop_pipe_ID.opc = "010000" else cop_pipe_ID.rt;
 	
 	im				<= status(15 downto 8);
@@ -148,7 +150,6 @@ exception_state:
 	process(exc_state, ctrl_in, cop_pipe_ID)
 	begin
 	
-		ctrl_out.exc_inject		<= '0';
 		ctrl_out.exc_commit		<= '0';
 		ctrl_out.exc_pending	<= '0';
 		ctrl_out.exc_exit 		<= '0';
@@ -156,6 +157,7 @@ exception_state:
 		code_reg_we				<= '0';	
 		status_save				<= '0';
 		status_rest				<= '0';
+		inject_exc				<= '0';
 		imem_addr_we			<= '0';
 
 		exc_staten	<= exc_state;
@@ -165,8 +167,8 @@ exception_state:
 		when exc_idle =>
 			if cop_pipe_ID.RFE = '1' then
 				exc_staten			<= exc_leave;
-				ctrl_out.exc_exit 		<= '1';
-				ctrl_out.exc_commit		<= '1';
+				ctrl_out.exc_exit 	<= '1';
+				ctrl_out.exc_commit	<= '1';
 			elsif ctrl_in.exc_req = '1' then
 				exc_staten			<= exc_pipe_flush;
 				imem_addr_we		<= '1';
@@ -188,11 +190,11 @@ exception_state:
 
 		when exc_inject =>
 			ctrl_out.exc_pending	<= '1';
-			ctrl_out.exc_inject		<= '1';
 			ctrl_out.exc_commit		<= '1';
 			code_reg_we				<= '1';
 			status_save				<= '1';
 			epc_reg_we				<= '1';
+			inject_exc				<= '1';
 			exc_staten				<= exc_enter;
 
 		when exc_enter =>
@@ -349,9 +351,15 @@ cop_exc_vector:
 	process(clk)
 	begin
 		if rising_edge(clk) then
-			ctrl_out.exc_vec		<= X"80000080";
-			if status(22) = '1' then
-				ctrl_out.exc_vec	<= X"BFC00180";
+			if rst = '1' then
+				inject_rst				<= '1';
+				ctrl_out.exc_vec		<= X"BFC00000";
+			else				
+				inject_rst				<= '0';
+				ctrl_out.exc_vec		<= X"80000080";
+				if status(22) = '1' then
+					ctrl_out.exc_vec	<= X"BFC00180";
+				end if;
 			end if;
 		end if;
 	end process;
@@ -409,9 +417,6 @@ cop_register_read:
 
 	end process;
 
--- 18296365000 ps
--- 20158175000 ps
-
 cop_we_gen:
 	process(clk)
 	begin
diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index a3d9edf..e9521c3 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -144,8 +144,6 @@ architecture Behavioral of pipeline is
 	END COMPONENT;
 
 --------------------------------------------------------------------------
-	constant RESET_VECTOR	: word_t := X"BFC00000";
-
 	signal ID_stage			: ID_t;
 	signal EX_stage			: EX_t;
 	signal MEM_stage		: MEM_t;
@@ -173,11 +171,6 @@ architecture Behavioral of pipeline is
 	signal stage_rst		: unsigned(3 downto 0);
 	signal pipe_rst			: STD_LOGIC;
 	
-	attribute ram_style : string;
-	
-	attribute ram_style of reg_a: signal is "distributed";
-	attribute ram_style of reg_b: signal is "distributed";
-
 	signal pc : pc_t;
 	
 --------------------------------------------------------------------------
@@ -279,28 +272,35 @@ proc_stage_pc_branch:
 		end if;	
 	end process;
 
-proc_stage_pc_next:
+proc_stage_branch_ce:
 	process(clk_1)
 	begin
 		if rising_edge(clk_1) then
 			if pipe_rst = '1' then
-				pc.nxt	<= RESET_VECTOR;
-				pc.last	<= RESET_VECTOR;
 				branch_ce	<= '1';
 			else
 				branch_ce	<= c0_ctrl_in.exc_pending;
-				if c0_ctrl_in.exc_inject = '1' then
-					pc.nxt	<= c0_ctrl_in.exc_vec;
-				elsif sdu.ID_stall = '0' then
+				if sdu.ID_stall = '0' then
 					branch_ce	<= '1';
-					pc.last	<= pc.curr;
-					if ID_stage.ctrl.jump = '1' then
-						pc.nxt	<= ID_stage.jimm32;
-					elsif ID_stage.ctrl.jump_long = '1' then
-						pc.nxt	<= ID_stage.reg_a;
-					else
-						pc.nxt	<= pc.curr + 4;
-					end if;
+				end if;
+			end if;
+		end if;	
+	end process;
+
+proc_stage_pc_next:
+	process(clk_1)
+	begin
+		if rising_edge(clk_1) then
+			if c0_ctrl_in.exc_inject = '1' then
+				pc.nxt	<= c0_ctrl_in.exc_vec;
+			elsif sdu.ID_stall = '0' then
+				pc.last	<= pc.curr;
+				if ID_stage.ctrl.jump = '1' then
+					pc.nxt	<= ID_stage.jimm32;
+				elsif ID_stage.ctrl.jump_long = '1' then
+					pc.nxt	<= ID_stage.reg_a;
+				else
+					pc.nxt	<= pc.curr + 4;
 				end if;
 			end if;
 		end if;