[BB-FIFO]

- fixed full and half full

git-svn-id: http://moon:8086/svn/vhdl/trunk@1350 cc03376c-175c-47c8-b038-4cd826a8556b

lib/misc/bbfifo.vhd

@@ -31,8 +31,8 @@ use IEEE.numeric_std.ALL;
 entity bbfifo is
 	Generic 
 	(
-		depth	   : integer := 2;
-		data_width : integer := 8
+		depth_bits	: integer := 4;
+		data_width	: integer := 8
 	);
 	Port
 	(
@@ -49,52 +49,83 @@ entity bbfifo is
 end bbfifo;
 
 architecture Behavioral of bbfifo is
-
+	
+	constant depth			: natural := 2**depth_bits;
 	type bucket_array_t is array (0 to depth) of unsigned(data_width-1 downto 0);
 	signal bucket_array 	: bucket_array_t; 
-	signal Q				: unsigned(0 to depth)		:= (others => '0');
-	signal ce				: unsigned(1 to depth+1)		:= (others => '0');
+	signal Q				: unsigned(0 to depth);
+	signal ce				: unsigned(1 to depth+1);
+	signal up				: std_logic;
+	signal down				: std_logic;
+	signal fill				: unsigned(depth_bits downto 0);
+	signal full_s			: std_logic;
 	
 begin
 	
 	Q(0)			<= we;
 	ce(depth+1)		<= re;
-	full			<= not ce(1);
-	half_full		<= not ce(1+depth/2);
+	full			<= full_s;
 	dout_vld		<= Q(depth);
 	bucket_array(0)	<= din;
 	dout			<= bucket_array(depth);
 	
+	up 				<= we and not full_s;
+	down			<= re and Q(depth);
+
+proc_fill:
+process(clk)
+variable fill_next : unsigned(depth_bits downto 0);
+begin
+	if rising_edge(clk) then
+		if rst = '1' then
+			fill_next	:= (others => '0');
+		elsif up = '1' and down = '0' then
+			fill_next	:= fill + 1;
+		elsif up = '0' and down = '1' then
+			fill_next	:= fill - 1;
+		end if;
+		full_s		<= '0';
+		half_full	<= '0';
+		fill		<= fill_next;
+		if fill_next > depth/2-1 then  
+			half_full	<= '1';
+		end if;
+		if fill_next > depth-1 then  
+			full_s	<= '1';
+		end if;
+	end if;
+end process;
+	
 gen_bb:
-	for i in 1 to depth generate
-		proc_ce:
-		process(Q, ce)
-		begin
-			ce(i) <= not Q(i) or ce(i+1);
-		end process;
+for i in 1 to depth generate
+	proc_ce:
+	process(Q, ce)
+	begin
+		ce(i) <= not Q(i) or ce(i+1);
+	end process;
 
-		proc_q:
-		process(clk)
-		begin
-			if rising_edge(clk) then
-				if rst = '1' then
-					Q(i)	<= '0';
-				elsif ce(i) = '1' then
-					Q(i)	<= Q(i-1);
-				end if;
+	proc_q:
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				Q(i)	<= '0';
+			elsif ce(i) = '1' then
+				Q(i)	<= Q(i-1);
 			end if;
-		end process;
+		end if;
+	end process;
 
-		proc_data:
-		process (clk)
-		begin
-			if rising_edge(clk) then
-				if ce(i) = '1' then
-					bucket_array(i) <= bucket_array(i-1);
-				end if;
+	proc_data:
+	process (clk)
+	begin
+		if rising_edge(clk) then
+			if ce(i) = '1' then
+				bucket_array(i) <= bucket_array(i-1);
 			end if;
-		end process;
-	end generate;
+		end if;
+	end process;
+end generate;
 
 end Behavioral;
 

lib/misc/sim/tb_bbfifo.wdo

@@ -14,8 +14,9 @@ add wave -noupdate -divider BB-FIFO
 add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/ce
 add wave -noupdate -format Literal /tb_bbfifo/inst_bbfifo/q
 add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/inst_bbfifo/bucket_array
+add wave -noupdate -format Literal -radix unsigned /tb_bbfifo/inst_bbfifo/fill
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {70000 ps} 0}
+WaveRestoreCursors {{Cursor 1} {77874 ps} 0}
 configure wave -namecolwidth 150
 configure wave -valuecolwidth 100
 configure wave -justifyvalue left

lib/misc/tb_bbfifo.vhd

@@ -50,7 +50,7 @@ begin
 inst_bbfifo : entity work.bbfifo
 	GENERIC MAP 
 	(
-		depth		=> 4,
+		depth_bits	=> 2,
 		data_width	=> 8
 	)
 	PORT MAP