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[BB-FIFO]

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- renamed ports
- added quick 'n dirty half full

git-svn-id: http://moon:8086/svn/vhdl/trunk@1349 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-19 18:55:37 +00:00
parent 4cd0065434
commit b8b6cfcd81
3 changed files with 40 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/misc/bbfifo.vhd
+6 -4
View File
@@ -40,8 +40,9 @@ entity bbfifo is
clk : in STD_LOGIC;
re : in STD_LOGIC;
we : in STD_LOGIC;
ready : out STD_LOGIC;
avail : out STD_LOGIC;
full : out STD_LOGIC;
half_full : out STD_LOGIC;
dout_vld : out STD_LOGIC;
din : in unsigned(data_width-1 downto 0);
dout : out unsigned(data_width-1 downto 0)
);
@@ -58,8 +59,9 @@ begin
Q(0) <= we;
ce(depth+1) <= re;
ready <= ce(1);
avail <= Q(depth);
full <= not ce(1);
half_full <= not ce(1+depth/2);
dout_vld <= Q(depth);
bucket_array(0) <= din;
dout <= bucket_array(depth);
lib/misc/sim/tb_bbfifo.wdo
+3 -2
View File
@@ -4,9 +4,10 @@ add wave -noupdate -format Logic /tb_bbfifo/rst
add wave -noupdate -format Logic /tb_bbfifo/clk
add wave -noupdate -format Logic /tb_bbfifo/re
add wave -noupdate -format Logic /tb_bbfifo/we
add wave -noupdate -format Logic /tb_bbfifo/ready
add wave -noupdate -format Logic /tb_bbfifo/inst_bbfifo/full
add wave -noupdate -format Logic /tb_bbfifo/inst_bbfifo/half_full
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/din
add wave -noupdate -format Logic /tb_bbfifo/avail
add wave -noupdate -format Logic /tb_bbfifo/inst_bbfifo/dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout
add wave -noupdate -format Literal -radix hexadecimal /tb_bbfifo/dout_reg
add wave -noupdate -divider BB-FIFO
lib/misc/tb_bbfifo.vhd
+31 -29
View File
@@ -37,8 +37,9 @@ architecture behave of tb_bbfifo is
signal clk : std_logic := '1';
signal re : std_logic := '0';
signal we : std_logic := '0';
signal ready : std_logic;
signal avail : std_logic;
signal dout_vld : std_logic;
signal full : std_logic;
signal half_full : std_logic;
signal din : unsigned(7 downto 0) := (others => '0');
signal dout : unsigned(7 downto 0);
signal dout_reg : unsigned(7 downto 0);
@@ -54,14 +55,15 @@ inst_bbfifo : entity work.bbfifo
)
PORT MAP
(
rst => rst,
clk => clk,
re => re,
we => we,
ready => ready,
avail => avail,
din => din,
dout => dout
rst => rst,
clk => clk,
re => re,
we => we,
full => full,
half_full => half_full,
dout_vld => dout_vld,
din => din,
dout => dout
);
@@ -74,7 +76,7 @@ CLK_GEN: process
RE_GEN: process
begin
wait for 2*CLK_PERIOD;
wait until rising_edge(clk) and avail = '1';
wait until rising_edge(clk) and dout_vld = '1';
re <= '1';
dout_reg <= dout;
wait until rising_edge(clk);
@@ -91,45 +93,45 @@ STIMULUS: process
wait for 3*CLK_PERIOD;
rst <= '0';
din <= X"10";
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '0';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '0';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
wait until rising_edge(clk) and full = '0';
wait until rising_edge(clk) and full = '0';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '1';
din <= din + 1;
wait until rising_edge(clk) and ready = '1';
wait until rising_edge(clk) and full = '0';
we <= '0';