- added extra register for bus master fifos

git-svn-id: http://moon:8086/svn/vhdl/trunk@1615 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-31 12:07:35 +00:00
parent 9360547eab
commit 8af5e1a8a5
2 changed files with 4 additions and 2 deletions
@@ -329,7 +329,8 @@ inst_bout_fifo: entity work.fifo_async
 	(
 		addr_width			=> 4,
 		data_width			=> 69,
-		do_last_read_update	=> false
+		do_last_read_update	=> false,
+		add_extra_read_register => true
 	)
 	PORT MAP
 	(
@@ -514,7 +514,8 @@ inst_busout_fifo: entity work.fifo_sync
 	(
 		addr_width			=> 2,
 		data_width			=> busout_fifo_din'length,
-		do_last_read_update	=> false
+		do_last_read_update	=> false,
+		add_extra_read_register => true
 	)
 	PORT MAP
 	(