From 8af5e1a8a5aceee76b67ccf7c32ce0a0e5233012 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 31 Mar 2021 12:07:35 +0000 Subject: [PATCH] - added extra register for bus master fifos git-svn-id: http://moon:8086/svn/vhdl/trunk@1615 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/src/core/mips_biu.vhd | 3 ++- lib/VGA_ctrl/src/vga_frontend_jb64.vhd | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/lib/CPUs/MIPS/src/core/mips_biu.vhd b/lib/CPUs/MIPS/src/core/mips_biu.vhd index e9b10ce..906488d 100644 --- a/lib/CPUs/MIPS/src/core/mips_biu.vhd +++ b/lib/CPUs/MIPS/src/core/mips_biu.vhd @@ -329,7 +329,8 @@ inst_bout_fifo: entity work.fifo_async ( addr_width => 4, data_width => 69, - do_last_read_update => false + do_last_read_update => false, + add_extra_read_register => true ) PORT MAP ( diff --git a/lib/VGA_ctrl/src/vga_frontend_jb64.vhd b/lib/VGA_ctrl/src/vga_frontend_jb64.vhd index 3008bee..ff9fac2 100644 --- a/lib/VGA_ctrl/src/vga_frontend_jb64.vhd +++ b/lib/VGA_ctrl/src/vga_frontend_jb64.vhd @@ -514,7 +514,8 @@ inst_busout_fifo: entity work.fifo_sync ( addr_width => 2, data_width => busout_fifo_din'length, - do_last_read_update => false + do_last_read_update => false, + add_extra_read_register => true ) PORT MAP (