[JUART]

- renamed ports

git-svn-id: http://moon:8086/svn/vhdl/trunk@1351 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/tb_juart_tx.vhd

@@ -37,25 +37,25 @@ architecture behave of tb_juart_tx is
 	signal rst				: std_logic := '1';  
 	signal clk				: std_logic := '1';  
 	signal en_16_x_baud		: std_logic := '1';  
-	signal send_character	: std_logic := '0';  
-	signal serial_out		: std_logic;  
+	signal we				: std_logic := '0';  
+	signal ser_out			: std_logic;  
 	signal Tx_complete		: std_logic;  
-	signal data_in			: unsigned(7 downto 0) := (others => '0');
+	signal din				: unsigned(7 downto 0) := (others => '0');
 
 	signal baud_count		: unsigned(15 downto 0);
 	signal baud_reg			: unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length);
 begin
 
-inst_juart_tx : entity work.juart_tx
+dut : entity work.juart_tx
 	PORT MAP
 	(
 		rst					=> rst,
 		clk					=> clk,
+		we					=> we,
+		din					=> din,
 		en_16_x_baud		=> en_16_x_baud,
-		send_character		=> send_character,
 		Tx_complete			=> Tx_complete,
-		data_in				=> data_in,
-		serial_out			=> serial_out
+		ser_out				=> ser_out
 	);
 
 
@@ -92,22 +92,22 @@ STIMULUS: process
 		rst <= '0';
 		wait for 3*CLK_PERIOD;
 		wait until rising_edge(clk);
-		data_in <= X"A5";
+		din <= X"A5";
 		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
+		we <= '1';
 		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
+		we <= '0';
 		wait until rising_edge(clk) and Tx_complete = '1';
-		data_in <= X"AA";
+		din <= X"AA";
 		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
+		we <= '1';
 		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
-		data_in <= X"55";
+		we <= '0';
+		din <= X"55";
 		wait until rising_edge(clk) and Tx_complete = '1';
-		send_character <= '1';
+		we <= '1';
 		wait until rising_edge(clk) and Tx_complete = '0';
-		send_character <= '0';
+		we <= '0';
 		wait; 
 	
 	end process;