From 82a500a99b0a82c9694042204d2a838803a9f075 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 20 Dec 2016 19:09:45 +0000 Subject: [PATCH] [JUART] - renamed ports git-svn-id: http://moon:8086/svn/vhdl/trunk@1351 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/uart/juart_rx.vhd | 33 ++++++++++++++++++--------------- lib/uart/juart_tx.vhd | 26 ++++++++++++++------------ lib/uart/sim/tb_juart_rx.wdo | 28 ++++++++++++++-------------- lib/uart/sim/tb_juart_tx.wdo | 20 ++++++++++---------- lib/uart/tb_juart_rx.vhd | 30 +++++++++++++++--------------- lib/uart/tb_juart_tx.vhd | 32 ++++++++++++++++---------------- 6 files changed, 87 insertions(+), 82 deletions(-) diff --git a/lib/uart/juart_rx.vhd b/lib/uart/juart_rx.vhd index 9295369..1d112f3 100644 --- a/lib/uart/juart_rx.vhd +++ b/lib/uart/juart_rx.vhd @@ -19,13 +19,16 @@ use IEEE.numeric_std.ALL; -- Main Entity -- entity juart_rx is - Port ( serial_in : in std_logic; - data_out : out unsigned(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic; - rst : in std_logic); - end juart_rx; + Port + ( + rst : in std_logic; + clk : in std_logic; + ser_in : in std_logic; + dout : out unsigned(7 downto 0); + dout_vld : out std_logic; + en_16_x_baud : in std_logic + ); +end juart_rx; -- ------------------------------------------------------------------------------------ -- @@ -72,10 +75,10 @@ data_out_reg: process(clk) begin if rising_edge(clk) then - data_strobe <= '0'; + dout_vld <= '0'; if data_valid = '1' then - data_out <= shiftreg; - data_strobe <= '1'; + dout <= shiftreg; + dout_vld <= '1'; end if; end if; end process; @@ -85,7 +88,7 @@ process(clk) begin if rising_edge(clk) then if rst = '1' then - state <= idle; + state <= idle; else state <= state_next; end if; @@ -93,7 +96,7 @@ begin end process; statemachine: -process(state, is_idle, bit_count, bit_sample, serial_in) +process(state, is_idle, bit_count, bit_sample, ser_in) begin state_next <= state; sample_count_rst <= '1'; @@ -107,7 +110,7 @@ begin state_next <= wait_start; end if; when wait_start => - if serial_in = '0' then + if ser_in = '0' then sample_count_rst <= '0'; state_next <= start; end if; @@ -139,7 +142,7 @@ begin if rst = '1' then shiftreg <= (others => '0'); elsif shiftreg_en = '1' and bit_sample = '1' and en_16_x_baud = '1' then - shiftreg <= shiftreg(shiftreg'left-1 downto 0) & serial_in; + shiftreg <= shiftreg(shiftreg'left-1 downto 0) & ser_in; end if; end if; end process; @@ -172,7 +175,7 @@ idle_detector: process(clk) begin if rising_edge(clk) then - if serial_in = '0' then + if ser_in = '0' then idle_count <= idle_count_t'high; elsif idle_count /= 0 and en_16_x_baud = '1' then idle_count <= idle_count - 1; diff --git a/lib/uart/juart_tx.vhd b/lib/uart/juart_tx.vhd index b2d369f..5ecb0a7 100644 --- a/lib/uart/juart_tx.vhd +++ b/lib/uart/juart_tx.vhd @@ -14,15 +14,17 @@ use IEEE.numeric_std.ALL; -- Main Entity -- entity juart_tx is - Port ( data_in : in unsigned(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic; - rst : in std_logic - ); - end juart_tx; + Port + ( + rst : in std_logic; + clk : in std_logic; + we : in std_logic; + din : in unsigned(7 downto 0); + en_16_x_baud : in std_logic; + Tx_complete : out std_logic; + ser_out : out std_logic + ); +end juart_tx; -- ------------------------------------------------------------------------------------ -- @@ -49,7 +51,7 @@ signal bit_count : unsigned (3 downto 0); -- -- begin -serial_out <= shiftreg(shiftreg'left); +ser_out <= shiftreg(shiftreg'left); Tx_complete <= not busy; shift_enable_counter: @@ -93,10 +95,10 @@ begin busy <= '0'; start <= '0'; elsif busy = '0' then - if send_character = '1' then + if we = '1' then busy <= '1'; start <= '1'; - dinreg <= data_in; + dinreg <= din; end if; elsif shift_enable = '1' then if start = '1' then diff --git a/lib/uart/sim/tb_juart_rx.wdo b/lib/uart/sim/tb_juart_rx.wdo index 889e39b..d5dcdc2 100644 --- a/lib/uart/sim/tb_juart_rx.wdo +++ b/lib/uart/sim/tb_juart_rx.wdo @@ -3,22 +3,22 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate -format Logic /tb_juart_rx/rst add wave -noupdate -format Logic /tb_juart_rx/clk add wave -noupdate -format Logic /tb_juart_rx/en_16_x_baud -add wave -noupdate -format Logic /tb_juart_rx/serial_in -add wave -noupdate -format Logic /tb_juart_rx/data_strobe +add wave -noupdate -format Logic /tb_juart_rx/ser_in +add wave -noupdate -format Logic /tb_juart_rx/dout_vld add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/data_reg add wave -noupdate -divider {JUART RX} -add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/bit_sample -add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/inst_juart_rx/bit_count -add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/inst_juart_rx/shiftreg -add wave -noupdate -format Literal /tb_juart_rx/inst_juart_rx/sample_count -add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/is_idle -add wave -noupdate -format Literal /tb_juart_rx/inst_juart_rx/state -add wave -noupdate -format Literal /tb_juart_rx/inst_juart_rx/state_next -add wave -noupdate -format Literal /tb_juart_rx/inst_juart_rx/idle_count -add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/bit_count_rst -add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/sample_count_rst -add wave -noupdate -format Logic /tb_juart_rx/inst_juart_rx/data_strobe -add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/data_out +add wave -noupdate -format Logic /tb_juart_rx/dut/bit_sample +add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/bit_count +add wave -noupdate -format Literal -radix unsigned /tb_juart_rx/dut/shiftreg +add wave -noupdate -format Literal /tb_juart_rx/dut/sample_count +add wave -noupdate -format Logic /tb_juart_rx/dut/is_idle +add wave -noupdate -format Literal /tb_juart_rx/dut/state +add wave -noupdate -format Literal /tb_juart_rx/dut/state_next +add wave -noupdate -format Literal /tb_juart_rx/dut/idle_count +add wave -noupdate -format Logic /tb_juart_rx/dut/bit_count_rst +add wave -noupdate -format Logic /tb_juart_rx/dut/sample_count_rst +add wave -noupdate -format Logic /tb_juart_rx/dut/dout_vld +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_rx/dout TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {5936632 ps} 0} configure wave -namecolwidth 150 diff --git a/lib/uart/sim/tb_juart_tx.wdo b/lib/uart/sim/tb_juart_tx.wdo index d227228..3718f9b 100644 --- a/lib/uart/sim/tb_juart_tx.wdo +++ b/lib/uart/sim/tb_juart_tx.wdo @@ -3,18 +3,18 @@ quietly WaveActivateNextPane {} 0 add wave -noupdate -format Logic /tb_juart_tx/rst add wave -noupdate -format Logic /tb_juart_tx/clk add wave -noupdate -format Logic /tb_juart_tx/en_16_x_baud -add wave -noupdate -format Logic /tb_juart_tx/send_character -add wave -noupdate -format Logic /tb_juart_tx/serial_out +add wave -noupdate -format Logic /tb_juart_tx/we +add wave -noupdate -format Logic /tb_juart_tx/ser_out add wave -noupdate -format Logic /tb_juart_tx/tx_complete -add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/data_in +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/din add wave -noupdate -divider JUART_TX -add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/inst_juart_tx/shiftreg -add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/inst_juart_tx/dinreg -add wave -noupdate -format Logic /tb_juart_tx/inst_juart_tx/start -add wave -noupdate -format Logic /tb_juart_tx/inst_juart_tx/busy -add wave -noupdate -format Logic /tb_juart_tx/inst_juart_tx/shift_enable -add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/inst_juart_tx/shift_enable_count -add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/inst_juart_tx/bit_count +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/dut/shiftreg +add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx/dut/dinreg +add wave -noupdate -format Logic /tb_juart_tx/dut/start +add wave -noupdate -format Logic /tb_juart_tx/dut/busy +add wave -noupdate -format Logic /tb_juart_tx/dut/shift_enable +add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/dut/shift_enable_count +add wave -noupdate -format Literal -radix unsigned /tb_juart_tx/dut/bit_count TreeUpdate [SetDefaultTree] WaveRestoreCursors {{Cursor 1} {9812114 ps} 0} configure wave -namecolwidth 150 diff --git a/lib/uart/tb_juart_rx.vhd b/lib/uart/tb_juart_rx.vhd index 5920829..bc35a13 100644 --- a/lib/uart/tb_juart_rx.vhd +++ b/lib/uart/tb_juart_rx.vhd @@ -37,9 +37,9 @@ architecture behave of tb_juart_rx is signal rst : std_logic := '1'; signal clk : std_logic := '1'; signal en_16_x_baud : std_logic := '1'; - signal serial_in : std_logic := '1'; - signal data_strobe : std_logic; - signal data_out : unsigned(7 downto 0); + signal ser_in : std_logic := '1'; + signal dout_vld : std_logic; + signal dout : unsigned(7 downto 0); signal serial_word : unsigned(7 downto 0) := X"AA"; signal baud_count : unsigned(15 downto 0); @@ -47,15 +47,15 @@ architecture behave of tb_juart_rx is signal data_reg : unsigned(7 downto 0); begin -inst_juart_rx : entity work.juart_rx +dut : entity work.juart_rx PORT MAP ( rst => rst, clk => clk, en_16_x_baud => en_16_x_baud, - data_strobe => data_strobe, - data_out => data_out, - serial_in => serial_in + dout_vld => dout_vld, + dout => dout, + ser_in => ser_in ); @@ -67,8 +67,8 @@ CLK_GEN: process PROC_DATAREG: process begin - wait until rising_edge(clk) and data_strobe = '1'; - data_reg <= data_out; + wait until rising_edge(clk) and dout_vld = '1'; + data_reg <= dout; end process; baud_timer: @@ -99,23 +99,23 @@ STIMULUS: process serial_word <= X"AA"; wait for 16*baud_div*CLK_PERIOD; - serial_in <= '0'; + ser_in <= '0'; wait for 16*baud_div*CLK_PERIOD; for i in serial_word'length-1 downto 0 loop - serial_in <= serial_word(i); + ser_in <= serial_word(i); wait for 16*baud_div*CLK_PERIOD; end loop; - serial_in <= '1'; + ser_in <= '1'; wait for 16*baud_div*CLK_PERIOD; serial_word <= X"55"; - serial_in <= '0'; + ser_in <= '0'; wait for 16*baud_div*CLK_PERIOD; for i in serial_word'length-1 downto 0 loop - serial_in <= serial_word(i); + ser_in <= serial_word(i); wait for 16*baud_div*CLK_PERIOD; end loop; - serial_in <= '1'; + ser_in <= '1'; wait; end process; diff --git a/lib/uart/tb_juart_tx.vhd b/lib/uart/tb_juart_tx.vhd index ca0f1f4..7815992 100644 --- a/lib/uart/tb_juart_tx.vhd +++ b/lib/uart/tb_juart_tx.vhd @@ -37,25 +37,25 @@ architecture behave of tb_juart_tx is signal rst : std_logic := '1'; signal clk : std_logic := '1'; signal en_16_x_baud : std_logic := '1'; - signal send_character : std_logic := '0'; - signal serial_out : std_logic; + signal we : std_logic := '0'; + signal ser_out : std_logic; signal Tx_complete : std_logic; - signal data_in : unsigned(7 downto 0) := (others => '0'); + signal din : unsigned(7 downto 0) := (others => '0'); signal baud_count : unsigned(15 downto 0); signal baud_reg : unsigned(15 downto 0) := to_unsigned(BAUD_DIV-1, baud_count'length); begin -inst_juart_tx : entity work.juart_tx +dut : entity work.juart_tx PORT MAP ( rst => rst, clk => clk, + we => we, + din => din, en_16_x_baud => en_16_x_baud, - send_character => send_character, Tx_complete => Tx_complete, - data_in => data_in, - serial_out => serial_out + ser_out => ser_out ); @@ -92,22 +92,22 @@ STIMULUS: process rst <= '0'; wait for 3*CLK_PERIOD; wait until rising_edge(clk); - data_in <= X"A5"; + din <= X"A5"; wait until rising_edge(clk) and Tx_complete = '1'; - send_character <= '1'; + we <= '1'; wait until rising_edge(clk) and Tx_complete = '0'; - send_character <= '0'; + we <= '0'; wait until rising_edge(clk) and Tx_complete = '1'; - data_in <= X"AA"; + din <= X"AA"; wait until rising_edge(clk) and Tx_complete = '1'; - send_character <= '1'; + we <= '1'; wait until rising_edge(clk) and Tx_complete = '0'; - send_character <= '0'; - data_in <= X"55"; + we <= '0'; + din <= X"55"; wait until rising_edge(clk) and Tx_complete = '1'; - send_character <= '1'; + we <= '1'; wait until rising_edge(clk) and Tx_complete = '0'; - send_character <= '0'; + we <= '0'; wait; end process;