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[JUART]

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- renamed ports

git-svn-id: http://moon:8086/svn/vhdl/trunk@1351 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-20 19:09:45 +00:00
parent 9522e9e22e
commit 82a500a99b
6 changed files with 87 additions and 82 deletions
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lib/uart/tb_juart_rx.vhd
+15 -15
View File
@@ -37,9 +37,9 @@ architecture behave of tb_juart_rx is
signal rst : std_logic := '1';
signal clk : std_logic := '1';
signal en_16_x_baud : std_logic := '1';
signal serial_in : std_logic := '1';
signal data_strobe : std_logic;
signal data_out : unsigned(7 downto 0);
signal ser_in : std_logic := '1';
signal dout_vld : std_logic;
signal dout : unsigned(7 downto 0);
signal serial_word : unsigned(7 downto 0) := X"AA";
signal baud_count : unsigned(15 downto 0);
@@ -47,15 +47,15 @@ architecture behave of tb_juart_rx is
signal data_reg : unsigned(7 downto 0);
begin
inst_juart_rx : entity work.juart_rx
dut : entity work.juart_rx
PORT MAP
(
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
data_strobe => data_strobe,
data_out => data_out,
serial_in => serial_in
dout_vld => dout_vld,
dout => dout,
ser_in => ser_in
);
@@ -67,8 +67,8 @@ CLK_GEN: process
PROC_DATAREG: process
begin
wait until rising_edge(clk) and data_strobe = '1';
data_reg <= data_out;
wait until rising_edge(clk) and dout_vld = '1';
data_reg <= dout;
end process;
baud_timer:
@@ -99,23 +99,23 @@ STIMULUS: process
serial_word <= X"AA";
wait for 16*baud_div*CLK_PERIOD;
serial_in <= '0';
ser_in <= '0';
wait for 16*baud_div*CLK_PERIOD;
for i in serial_word'length-1 downto 0 loop
serial_in <= serial_word(i);
ser_in <= serial_word(i);
wait for 16*baud_div*CLK_PERIOD;
end loop;
serial_in <= '1';
ser_in <= '1';
wait for 16*baud_div*CLK_PERIOD;
serial_word <= X"55";
serial_in <= '0';
ser_in <= '0';
wait for 16*baud_div*CLK_PERIOD;
for i in serial_word'length-1 downto 0 loop
serial_in <= serial_word(i);
ser_in <= serial_word(i);
wait for 16*baud_div*CLK_PERIOD;
end loop;
serial_in <= '1';
ser_in <= '1';
wait;
end process;