jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[JUART]

Browse Source 
- renamed ports

git-svn-id: http://moon:8086/svn/vhdl/trunk@1351 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-20 19:09:45 +00:00
parent 9522e9e22e
commit 82a500a99b
6 changed files with 87 additions and 82 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/juart_tx.vhd
+14 -12
View File
@@ -14,15 +14,17 @@ use IEEE.numeric_std.ALL;
-- Main Entity
--
entity juart_tx is
Port ( data_in : in unsigned(7 downto 0);
send_character : in std_logic;
en_16_x_baud : in std_logic;
serial_out : out std_logic;
Tx_complete : out std_logic;
clk : in std_logic;
rst : in std_logic
);
end juart_tx;
Port
(
rst : in std_logic;
clk : in std_logic;
we : in std_logic;
din : in unsigned(7 downto 0);
en_16_x_baud : in std_logic;
Tx_complete : out std_logic;
ser_out : out std_logic
);
end juart_tx;
--
------------------------------------------------------------------------------------
--
@@ -49,7 +51,7 @@ signal bit_count : unsigned (3 downto 0);
--
--
begin
serial_out <= shiftreg(shiftreg'left);
ser_out <= shiftreg(shiftreg'left);
Tx_complete <= not busy;
shift_enable_counter:
@@ -93,10 +95,10 @@ begin
busy <= '0';
start <= '0';
elsif busy = '0' then
if send_character = '1' then
if we = '1' then
busy <= '1';
start <= '1';
dinreg <= data_in;
dinreg <= din;
end if;
elsif shift_enable = '1' then
if start = '1' then