diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.par b/projects/mips_sys/ise101/mips_sys/mips_sys.par new file mode 100644 index 0000000..a46559a --- /dev/null +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.par @@ -0,0 +1,209 @@ +Release 10.1.03 par K.39 (nt) +Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. + +JUPITER:: Sun Feb 07 20:01:09 2010 + +par -w -intstyle ise -ol high -xe n -t 1 mips_sys_map.ncd mips_sys.ncd +mips_sys.pcf + + +Constraints file: mips_sys.pcf. +Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE. + "mips_sys" is an NCD, version 3.2, device xc4vsx35, package ff668, speed -10 +The STEPPING level for this design is ES. + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +Device speed data version: "PRODUCTION 1.68 2008-07-25". + + + +Device Utilization Summary: + + Number of BSCANs 1 out of 4 25% + Number of BUFGs 12 out of 32 37% + Number of DCM_ADVs 4 out of 8 50% + Number of ILOGICs 99 out of 448 22% + Number of External IOBs 226 out of 448 50% + Number of LOCed IOBs 226 out of 226 100% + + Number of OLOGICs 182 out of 448 40% + Number of RAMB16s 51 out of 192 26% + Number of Slices 5888 out of 15360 38% + Number of SLICEMs 561 out of 7680 7% + + + +Overall effort level (-ol): High +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 14 secs +Finished initial Timing Analysis. REAL time: 14 secs + +Starting Router + +Phase 1: 47772 unrouted; REAL time: 16 secs + +Phase 2: 40729 unrouted; REAL time: 16 secs + +Phase 3: 15700 unrouted; REAL time: 23 secs + +Phase 4: 15700 unrouted; (296275) REAL time: 23 secs + +Phase 5: 16428 unrouted; (12142) REAL time: 30 secs + +Phase 6: 16484 unrouted; (815) REAL time: 30 secs + +Phase 7: 0 unrouted; (10463) REAL time: 1 mins 3 secs + +Updating file: mips_sys.ncd with current fully routed design. + +Phase 8: 0 unrouted; (10463) REAL time: 2 mins 52 secs + +Phase 9: 0 unrouted; (6271) REAL time: 3 mins 5 secs + +Phase 10: 0 unrouted; (6221) REAL time: 3 mins 12 secs + +Phase 11: 0 unrouted; (6221) REAL time: 3 mins 12 secs + +Updating file: mips_sys.ncd with current fully routed design. + +Phase 12: 0 unrouted; (5742) REAL time: 4 mins 33 secs + +Phase 13: 0 unrouted; (5742) REAL time: 4 mins 48 secs + +Updating file: mips_sys.ncd with current fully routed design. + +Phase 14: 0 unrouted; (483) REAL time: 5 mins 13 secs + +Phase 15: 0 unrouted; (483) REAL time: 5 mins 18 secs + +Phase 16: 0 unrouted; (483) REAL time: 5 mins 23 secs + +Total REAL time to Router completion: 5 mins 26 secs +Total CPU time to Router completion: 5 mins 11 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| cpu_clk |BUFGCTRL_X0Y12| No | 1616 | 0.434 | 4.046 | ++---------------------+--------------+------+------+------------+-------------+ +| CLK_O | BUFGCTRL_X0Y2| No | 2299 | 0.544 | 3.933 | ++---------------------+--------------+------+------+------------+-------------+ +| vga_clk |BUFGCTRL_X0Y11| No | 170 | 0.400 | 3.881 | ++---------------------+--------------+------+------+------------+-------------+ +| sys_clk_in_IBUFG | BUFGCTRL_X0Y1| No | 67 | 0.241 | 3.697 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk0 |BUFGCTRL_X0Y31| No | 237 | 0.383 | 3.933 | ++---------------------+--------------+------+------+------------+-------------+ +|inst_rom_wb/inst_rom | | | | | | +| /bs_clk1 | BUFGCTRL_X0Y0| No | 71 | 0.159 | 3.562 | ++---------------------+--------------+------+------+------------+-------------+ +|sys_ac97_bit_clk_IBU | | | | | | +| F | BUFGCTRL_X0Y8| No | 253 | 0.397 | 3.865 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk270 |BUFGCTRL_X0Y16| No | 66 | 0.173 | 3.932 | ++---------------------+--------------+------+------+------------+-------------+ +| sdram_clk270var |BUFGCTRL_X0Y28| No | 32 | 0.025 | 3.930 | ++---------------------+--------------+------+------+------------+-------------+ +|inst_rom_wb/inst_rom | | | | | | +| /bs_update1 |BUFGCTRL_X0Y26| No | 4 | 0.035 | 3.487 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +Timing Score: 483 + +WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in + your design. + + Review the timing report using Timing Analyzer (In ISE select "Post-Place & + Route Static Timing Report"). Go to the failing constraint(s) and select + the "Timing Improvement Wizard" link for suggestions to correct each problem. + + Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to + ensure the best options are set in the tools for timing closure. + + Use the Xilinx "SmartXplorer" script to try special combinations of + options known to produce very good results. + +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no + requested value. +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +------------------------------------------------------------------------------------------------------ + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +------------------------------------------------------------------------------------------------------ +* TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 | SETUP | -0.118ns| 10.018ns| 5| 483 + ns HIGH 50% | HOLD | 0.383ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 n | SETUP | 0.010ns| 7.990ns| 0| 0 + s HIGH 50% | HOLD | 0.508ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" | SETUP | 0.072ns| 7.356ns| 0| 0 + 7.5 ns HIGH 50% | HOLD | 0.515ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns | SETUP | 0.164ns| 9.736ns| 0| 0 + HIGH 50% | HOLD | 0.326ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 | SETUP | 36.549ns| 6.902ns| 0| 0 + ns HIGH 50% | HOLD | 0.480ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 | SETUP | 74.795ns| 5.205ns| 0| 0 + ns HIGH 50% | HOLD | 0.824ns| | 0| 0 +------------------------------------------------------------------------------------------------------ + PATH "TS_unrelate_SDRAM_path" TIG | SETUP | N/A| 9.446ns| N/A| 0 +------------------------------------------------------------------------------------------------------ + PATH "TS_unrelate_VGA_path" TIG | SETUP | N/A| 6.486ns| N/A| 0 +------------------------------------------------------------------------------------------------------ + PATH "TS_unrelate_CPU_path" TIG | MAXDELAY| N/A| 8.192ns| N/A| 0 +------------------------------------------------------------------------------------------------------ + + +1 constraint not met. +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the + constraint does not cover any paths or that it has no requested value. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 5 mins 35 secs +Total CPU time to PAR completion: 5 mins 17 secs + +Peak Memory Usage: 418 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - 5 errors found. + +Number of error messages: 0 +Number of warning messages: 1 +Number of info messages: 1 + +Writing design to file mips_sys.ncd + + + +PAR done! diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.syr b/projects/mips_sys/ise101/mips_sys/mips_sys.syr new file mode 100644 index 0000000..e0a0056 --- /dev/null +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.syr @@ -0,0 +1,5197 @@ +Release 10.1.03 - xst K.39 (nt) +Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.08 secs + +--> Parameter xsthdpdir set to W:/vhdl/projects/mips_sys/ise101/mips_sys/xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.08 secs + +--> Reading design: mips_sys.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "mips_sys.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "mips_sys" +Output Format : NGC +Target Device : xc4vsx35-10-ff668 + +---- Source Options +Top Module Name : mips_sys +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : NO +Asynchronous To Synchronous : NO +Use DSP Block : auto +Automatic Register Balancing : Yes + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 32 +Number of Regional Clock Buffers : 24 +Register Duplication : YES +Move First FlipFlop Stage : YES +Move Last FlipFlop Stage : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : true +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Library Search Order : mips_sys.lso +Keep Hierarchy : NO +Netlist Hierarchy : as_optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_ctrl_pkg.vhd" in Library work. +Architecture fifo_ctrl_pkg of Entity fifo_ctrl_pkg is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_types.vhd" in Library work. +Architecture vga_types of Entity vga_types is up to date. +Compiling vhdl file "W:/vhdl/projects/mips_sys/src/sdram_config.vhd" in Library work. +Compiling vhdl file "W:/vhdl/lib/FIFO/src/gray_counter.vhd" in Library work. +Architecture behavioral of Entity gray_counter is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/singleshot.vhd" in Library work. +Architecture behavioral of Entity singleshot is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd" in Library work. +Architecture behavioral of Entity vga_sync is up to date. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd" in Library work. +Architecture sdram_types of Entity sdram_types is up to date. +Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd" in Library work. +Architecture behavioral of Entity fifo_async_ctrl is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/dpram_1w1r.vhd" in Library work. +Architecture behavioral of Entity dpram_1w1r is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/utils_pkg.vhd" in Library work. +Architecture utils_pkg of Entity utils_pkg is up to date. +Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" in Library work. +Architecture behavioral of Entity ac_in is up to date. +Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" in Library work. +Architecture behavioral of Entity ac_out is up to date. +Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd" in Library work. +Architecture behavioral of Entity fifo_sync_ctrl is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd" in Library work. +Architecture rtl of Entity char_rom is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd" in Library work. +Architecture behavioral of Entity vga_timing is up to date. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" in Library work. +Architecture behaviour of Entity sdram_ctrl is up to date. +Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_async.vhd" in Library work. +Architecture behavioral of Entity fifo_async is up to date. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" in Library work. +Architecture behaviour of Entity sdram_cmd is up to date. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" in Library work. +Architecture tech of Entity ddr_phy is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/kcuart_rx.vhd" in Library work. +Architecture low_level_definition of Entity kcuart_rx is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/bbfifo_16x8.vhd" in Library work. +Architecture low_level_definition of Entity bbfifo_16x8 is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/kcuart_tx.vhd" in Library work. +Architecture low_level_definition of Entity kcuart_tx is up to date. +Compiling vhdl file "W:/vhdl/lib/ps2_port/src/debounce.vhd" in Library work. +Architecture behavioral of Entity debounce is up to date. +Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" in Library work. +Architecture behavioral of Entity ps2_core is up to date. +Compiling vhdl file "W:/vhdl/lib/FIFO/src/fifo_sync.vhd" in Library work. +Architecture behavioral of Entity fifo_sync is up to date. +Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd" in Library work. +Architecture behavioral of Entity ac_io is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd" in Library work. +Architecture behavioral of Entity vga_backend is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd" in Library work. +Architecture behavioral of Entity char_gen is up to date. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" in Library work. +Architecture rtl of Entity sdram_ctrl_top is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/uart_tx.vhd" in Library work. +Architecture macro_level_definition of Entity uart_tx is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/uart_rx.vhd" in Library work. +Architecture macro_level_definition of Entity uart_rx is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/async_types.vhd" in Library work. +Architecture async_types of Entity async_types is up to date. +Compiling vhdl file "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd" in Library work. +Architecture data of Entity rom is up to date. +Compiling vhdl file "W:/vhdl/lib/CPUs/MIPS/src/core/mips_types.vhd" in Library work. +Architecture mips_types of Entity mips_types is up to date. +Compiling vhdl file "W:/vhdl/projects/mips_sys/src/async_defs.vhd" in Library work. +Compiling vhdl file "W:/vhdl/lib/misc/rom_wb.vhd" in Library work. +Architecture behavior of Entity rom_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/lcd_port.vhd" in Library work. +Architecture behavioral of Entity lcd_port is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/gpio_wb.vhd" in Library work. +Architecture behavior of Entity gpio_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/misc/async_port_wb.vhd" in Library work. +Architecture behavioral of Entity async_port_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/uart/uart_wb.vhd" in Library work. +Architecture behavior of Entity uart_wb is up to date. +Compiling vhdl file "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" in Library work. +Architecture struct of Entity sdram_ctrl_frontend64_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" in Library work. +Architecture behavioral of Entity vga_frontend64 is up to date. +Compiling vhdl file "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd" in Library work. +Architecture behavior of Entity ac97_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd" in Library work. +Architecture behavior of Entity ps2_wb is up to date. +Compiling vhdl file "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd" in Library work. +Architecture behavioral of Entity ps2_phy is up to date. +Compiling vhdl file "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" in Library work. +Architecture behavior of Entity mips_sys is up to date. + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for entity in library (architecture ) with generics. + ddr_frequency_hz = 100000000 + ddr_phaseshift = 0 + sys_freq = 100000000 + sys_freq_in = 100000000 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 25 + async_timespec = (T_leadin => 0.000000 + T_pulse_rd => 120.000000 + T_pulse_wr => 70.000000 + T_leadout => 0.000000 + T_release => 40.000000 + T_pulse_rst => 80.000000 + T_pulse_page_rd => 30.000000 + can_page_rd => true + nbits_page_rd => 4 + pol_cs => '1' + pol_oe => '0' + pol_we => '0' + pol_be => '0' + pol_rst => '0') + byte_sel_width = 1 + data_width = 32 + f_sysclk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 4 + async_timespec = (T_leadin => 10.000000 + T_pulse_rd => 60.000000 + T_pulse_wr => 60.000000 + T_leadout => 10.000000 + T_release => 80.000000 + T_pulse_rst => 80.000000 + T_pulse_page_rd => 0.000000 + can_page_rd => false + nbits_page_rd => 0 + pol_cs => '0' + pol_oe => '0' + pol_we => '0' + pol_be => '0' + pol_rst => '0') + byte_sel_width = 1 + data_width = 16 + f_sysclk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + clk_in_freq_hz = 100000000 + sdr0_clk_out_phaseshift = 0 + sdr1_clk_out_phaseshift = 0 + sys_clk_out_freq_hz = 100000000 + vga_clk_out_freq_hz = 40000000 + +Analyzing hierarchy for entity in library (architecture ) with generics. + BL = 2 + f_sdrclk_hz = 100000000 + f_sysclk_hz = 100000000 + fifo_depth = 5 + +Analyzing hierarchy for entity in library (architecture ) with generics. + fifo_almost_empty_thresh = 256 + fifo_almost_full_thresh = 1920 + fifo_depth = 2048 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + +Analyzing hierarchy for entity in library (architecture ) with generics. + fifo_depth = 8 + +Analyzing hierarchy for entity in library (architecture ) with generics. + f_sys_clk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 30 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 72 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + BL = 2 + f_sdrclk_hz = 100000000 + f_sysclk_hz = 100000000 + fifo_depth = 5 + +Analyzing hierarchy for entity in library (architecture ) with generics. + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 11 + almost_empty_thresh = 256 + almost_full_thresh = 1920 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 9 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 2 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 105 + +Analyzing hierarchy for entity in library (architecture ) with generics. + CHARACTER_SCALE = 1 + CHAR_ROM_DEPTH = 256 + CHAR_ROM_SIZE_X = 8 + CHAR_ROM_SIZE_Y = 16 + CHAR_SPACING_X = 0 + CHAR_SPACING_Y = 0 + MAX_CHAR_PER_LINE = 80 + MAX_LINE_PER_FRAME = 32 + SCREEN_OFFSET_X = 16 + SCREEN_OFFSET_Y = 16 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 8 + almost_empty_thresh = 25 + almost_full_thresh = 230 + data_width = 18 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + f_sys_clk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ) with generics. + ncyc_latency = 8 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + data_width = 30 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + data_width = 72 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + BL = 2 + f_sysclk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 32 + +Analyzing hierarchy for entity in library (architecture ) with generics. + BL = 2 + f_sdrclk_hz = 100000000 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 11 + almost_empty_thresh = 256 + almost_full_thresh = 1920 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 11 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 9 + almost_empty_thresh = 4 + almost_full_thresh = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 9 + data_width = 64 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 2 + almost_empty_thresh = 4 + almost_full_thresh = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 2 + data_width = 105 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 12 + data_width = 8 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 8 + almost_empty_thresh = 25 + almost_full_thresh = 230 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 8 + data_width = 18 + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ) with generics. + init_value = 0 + width = 6 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + addr_width = 5 + data_width = 32 + +Analyzing hierarchy for entity in library (architecture ) with generics. + ts = (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + +Analyzing hierarchy for entity in library (architecture ) with generics. + ts = (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0') + +Analyzing hierarchy for entity in library (architecture ) with generics. + init_value = 0 + width = 12 + +Analyzing hierarchy for entity in library (architecture ) with generics. + mode = 0 + +Analyzing hierarchy for entity in library (architecture ) with generics. + mode = 1 + +Analyzing hierarchy for entity in library (architecture ) with generics. + init_value = 0 + width = 6 + +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 221: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 270: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 318: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 257: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 254: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 133: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 281: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 300: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 354: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 158: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 215: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 226: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/bbfifo_16x8.vhd" line 239: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_rx.vhd" line 236: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. +WARNING:Xst:2591 - "W:/vhdl/lib/uart/kcuart_tx.vhd" line 333: attribute on instance overrides generic/parameter on component. It is possible that simulator will not take this attribute into account. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing generic Entity in library (Architecture ). + ddr_frequency_hz = 100000000 + ddr_phaseshift = 0 + sys_freq = 100000000 + sys_freq_in = 100000000 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) + Set user-defined property "KEEP = TRUE" for signal . + Set user-defined property "KEEP = TRUE" for signal . + Set user-defined property "KEEP = TRUE" for signal . + Set user-defined property "KEEP = TRUE" for signal . + Set user-defined property "KEEP = TRUE" for signal . +WARNING:Xst:2211 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 674: Instantiating black box module . +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 711: Unconnected output port 'dout' of component 'lcd_port'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 748: Unconnected output port 'async_be' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_be' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 781: Unconnected output port 'async_rst' of component 'async_port_wb'. +WARNING:Xst:753 - "W:/vhdl/projects/mips_sys/src/mips_sys.vhd" line 855: Unconnected output port 'sdr1_clk0_out' of component 'clockgen'. +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "JTAG_CHAIN = 1" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 25 + async_timespec = (T_leadin => 0.000000 + T_pulse_rd => 120.000000 + T_pulse_wr => 70.000000 + T_leadout => 0.000000 + T_release => 40.000000 + T_pulse_rst => 80.000000 + T_pulse_page_rd => 30.000000 + can_page_rd => true + nbits_page_rd => 4 + pol_cs => '1' + pol_oe => '0' + pol_we => '0' + pol_be => '0' + pol_rst => '0') + byte_sel_width = 1 + data_width = 32 + f_sysclk_hz = 100000000 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 4 + async_timespec = (T_leadin => 10.000000 + T_pulse_rd => 60.000000 + T_pulse_wr => 60.000000 + T_leadout => 10.000000 + T_release => 80.000000 + T_pulse_rst => 80.000000 + T_pulse_page_rd => 0.000000 + can_page_rd => false + nbits_page_rd => 0 + pol_cs => '0' + pol_oe => '0' + pol_we => '0' + pol_be => '0' + pol_rst => '0') + byte_sel_width = 1 + data_width = 16 + f_sysclk_hz = 100000000 +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "INIT = E4FF" for instance in unit . + Set user-defined property "INIT = E4FF" for instance in unit . + Set user-defined property "INIT = E4FF" for instance in unit . + Set user-defined property "INIT = E4FF" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 8" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 8" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 8" for instance in unit . + Set user-defined property "INIT = 10" for instance in unit . + Set user-defined property "INIT = 0190" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 1540" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 94" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0180" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 8" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 6606" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 6606" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 6606" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 6606" for instance in unit . + Set user-defined property "INIT = 0001" for instance in unit . + Set user-defined property "INIT = 8000" for instance in unit . + Set user-defined property "INIT = BFA0" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = C4" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0040" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 54" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 0000" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "INIT = 8" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + clk_in_freq_hz = 100000000 + sdr0_clk_out_phaseshift = 0 + sdr1_clk_out_phaseshift = 0 + sys_clk_out_freq_hz = 100000000 + vga_clk_out_freq_hz = 40000000 + Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 5" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 2" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . + Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = F0F0" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . + Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 2" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 2" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = NONE" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . + Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = F0F0" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . + Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = FIXED" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . + Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SOURCE_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = F0F0" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . + Set user-defined property "CLKDV_DIVIDE = 2.0000000000000000" for instance in unit . + Set user-defined property "CLKFX_DIVIDE = 1" for instance in unit . + Set user-defined property "CLKFX_MULTIPLY = 4" for instance in unit . + Set user-defined property "CLKIN_DIVIDE_BY_2 = FALSE" for instance in unit . + Set user-defined property "CLKIN_PERIOD = 10.0000000000000000" for instance in unit . + Set user-defined property "CLKOUT_PHASE_SHIFT = FIXED" for instance in unit . + Set user-defined property "CLK_FEEDBACK = 1X" for instance in unit . + Set user-defined property "DCM_AUTOCALIBRATION = TRUE" for instance in unit . + Set user-defined property "DCM_PERFORMANCE_MODE = MAX_SPEED" for instance in unit . + Set user-defined property "DESKEW_ADJUST = SYSTEM_SYNCHRONOUS" for instance in unit . + Set user-defined property "DFS_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DLL_FREQUENCY_MODE = LOW" for instance in unit . + Set user-defined property "DUTY_CYCLE_CORRECTION = TRUE" for instance in unit . + Set user-defined property "FACTORY_JF = F0F0" for instance in unit . + Set user-defined property "PHASE_SHIFT = 0" for instance in unit . + Set user-defined property "STARTUP_WAIT = FALSE" for instance in unit . +WARNING:Xst:819 - "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd" line 345: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: + , , , +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + BL = 2 + f_sdrclk_hz = 100000000 + f_sysclk_hz = 100000000 + fifo_depth = 5 +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_afull' of component 'fifo_sync'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 139: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_afull' of component 'fifo_async'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 160: Unconnected output port 'fifo_aempty' of component 'fifo_async'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_afull' of component 'fifo_async'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" line 182: Unconnected output port 'fifo_aempty' of component 'fifo_async'. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 30 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + data_width = 30 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 72 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + init_value = 0 + width = 6 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + data_width = 72 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + BL = 2 + f_sdrclk_hz = 100000000 + f_sysclk_hz = 100000000 + fifo_depth = 5 +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_afull' of component 'fifo_async'. +WARNING:Xst:753 - "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" line 158: Unconnected output port 'fifo_aempty' of component 'fifo_async'. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + BL = 2 + f_sysclk_hz = 100000000 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 32 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 5 + data_width = 32 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + BL = 2 + f_sdrclk_hz = 100000000 +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = OPPOSITE_EDGE" for instance in unit . + Set user-defined property "INIT = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . + Set user-defined property "DDR_CLK_EDGE = SAME_EDGE" for instance in unit . + Set user-defined property "INIT_Q1 = 0" for instance in unit . + Set user-defined property "INIT_Q2 = 0" for instance in unit . + Set user-defined property "SRTYPE = SYNC" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + fifo_almost_empty_thresh = 256 + fifo_almost_full_thresh = 1920 + fifo_depth = 2048 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) +WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_afull' of component 'fifo_sync'. +WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 366: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. +WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_afull' of component 'fifo_sync'. +WARNING:Xst:753 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 392: Unconnected output port 'fifo_aempty' of component 'fifo_sync'. +WARNING:Xst:819 - "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd" line 435: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: + +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + ts = (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + ts = (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0') +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 11 + almost_empty_thresh = 256 + almost_full_thresh = 1920 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 11 + almost_empty_thresh = 256 + almost_full_thresh = 1920 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + init_value = 0 + width = 12 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 11 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 9 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 9 + almost_empty_thresh = 4 + almost_full_thresh = 12 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 9 + data_width = 64 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 2 + almost_empty_thresh = 4 + almost_full_thresh = 12 + data_width = 105 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 2 + almost_empty_thresh = 4 + almost_full_thresh = 12 +INFO:Xst:2679 - Register in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 2 + data_width = 105 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + CHARACTER_SCALE = 1 + CHAR_ROM_DEPTH = 256 + CHAR_ROM_SIZE_X = 8 + CHAR_ROM_SIZE_Y = 16 + CHAR_SPACING_X = 0 + CHAR_SPACING_Y = 0 + MAX_CHAR_PER_LINE = 80 + MAX_LINE_PER_FRAME = 32 + SCREEN_OFFSET_X = 16 + SCREEN_OFFSET_Y = 16 + tsvga = (f_pxl_clk => 40000000 + nfps => 60 + ts_h => (ncyc_scan => 800 + ncyc_porch_front => 40 + ncyc_sync_pulse => 128 + ncyc_porch_back => 88 + sync_polarity => '0') + ts_v => (ncyc_scan => 600 + ncyc_porch_front => 1 + ncyc_sync_pulse => 4 + ncyc_porch_back => 23 + sync_polarity => '0')) +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 12 + data_width = 8 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + fifo_depth = 8 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 8 + almost_empty_thresh = 25 + almost_full_thresh = 230 + data_width = 18 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 8 + almost_empty_thresh = 25 + almost_full_thresh = 230 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + addr_width = 8 + data_width = 18 +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd" line 128: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + mode = 0 +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + mode = 1 +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). +WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 127: Index value(s) does not match array range, simulation mismatch. +WARNING:Xst:790 - "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd" line 128: Index value(s) does not match array range, simulation mismatch. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + f_sys_clk_hz = 100000000 +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +INFO:Xst:2679 - Register > in unit has a constant value of 0 during circuit operation. The register is replaced by logic. +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + f_sys_clk_hz = 100000000 +WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 191: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: + +WARNING:Xst:819 - "W:/vhdl/lib/ps2_port/src/ps2_core.vhd" line 204: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: + +Entity analyzed. Unit generated. + +Analyzing Entity in library (Architecture ). + Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit . + Set user-defined property "DRIVE = 2" for instance in unit . + Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit . + Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit . + Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit . + Set user-defined property "SLEW = SLOW" for instance in unit . + Set user-defined property "CAPACITANCE = DONT_CARE" for instance in unit . + Set user-defined property "DRIVE = 2" for instance in unit . + Set user-defined property "IBUF_DELAY_VALUE = 0" for instance in unit . + Set user-defined property "IFD_DELAY_VALUE = AUTO" for instance in unit . + Set user-defined property "IOSTANDARD = DEFAULT" for instance in unit . + Set user-defined property "SLEW = SLOW" for instance in unit . +Entity analyzed. Unit generated. + +Analyzing generic Entity in library (Architecture ). + ncyc_latency = 8 +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/lcd_port.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 4-bit tristate buffer for signal . + Found 8-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 15 D-type flip-flop(s). + inferred 4 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/gpio_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit comparator less for signal created at line 254. + Found 1-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator greatequal for signal created at line 254. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 7-bit up counter for signal . + Found 7-bit comparator greatequal for signal created at line 236. + Found 64-bit register for signal . + Found 2-bit register for signal . + Found 32-bit up counter for signal . + Found 32-bit comparator greatequal for signal created at line 291. + Found 32-bit comparator greatequal for signal created at line 291. + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 32-bit comparator less for signal created at line 291. + Found 32-bit comparator less for signal created at line 291. + Summary: + inferred 5 Counter(s). + inferred 339 D-type flip-flop(s). + inferred 7 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 15 | + | Inputs | 3 | + | Outputs | 6 | + | Clock | CLK_I (rising_edge) | + | Reset | RST_I (positive) | + | Reset type | synchronous | + | Reset State | start | + | Power Up State | start | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found 32-bit tristate buffer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 25-bit register for signal . + Found 4-bit down counter for signal . + Found 32-bit register for signal . + Found 21-bit comparator equal for signal created at line 83. + Found 32-bit register for signal created at line 310. + Found 1-bit register for signal created at line 310. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 Counter(s). + inferred 155 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 32 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/async_port_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:1305 - Output > is never assigned. Tied to value 0000000000000000. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 7 | + | Transitions | 13 | + | Inputs | 2 | + | Outputs | 6 | + | Clock | CLK_I (rising_edge) | + | Reset | RST_I (positive) | + | Reset type | synchronous | + | Reset State | start | + | Power Up State | start | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 16-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 16-bit tristate buffer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit down counter for signal . + Found 16-bit register for signal . + Found 16-bit register for signal created at line 310. + Found 1-bit register for signal created at line 310. + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 Counter(s). + inferred 61 D-type flip-flop(s). + inferred 16 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit updown counter for signal . + Found 1-bit register for signal . + Found 6-bit comparator lessequal for signal created at line 108. + Found 6-bit comparator greatequal for signal created at line 94. + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit adder for signal created at line 196. + Found 5-bit comparator equal for signal created at line 144. + Found 5-bit comparator equal for signal created at line 139. + Found 5-bit register for signal . + Found 5-bit adder for signal created at line 178. + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 15 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 32x30-bit dual-port RAM for signal . + Found 30-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 30 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 32x72-bit dual-port RAM for signal . + Found 72-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 72 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit adder for signal created at line 80. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Summary: + inferred 18 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 32x64-bit dual-port RAM for signal . + Found 64-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 13 | + | Transitions | 37 | + | Inputs | 12 | + | Outputs | 15 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | asynchronous | + | Reset State | reset | + | Power Up State | reset | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 15x27-bit ROM for signal <$rom0000>. + Found 4-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 9-bit register for signal . + Found 8-bit down counter for signal . + Found 1-bit register for signal . + Found 15-bit down counter for signal . + Found 1-bit register for signal . + Found 10-bit down counter for signal . + Found 1-bit register for signal . + Found 13-bit register for signal . + Found 13-bit register for signal . + Found 5-bit up counter for signal . + Found 13-bit comparator not equal for signal created at line 264. + Found 4-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 ROM(s). + inferred 4 Counter(s). + inferred 50 D-type flip-flop(s). + inferred 1 Comparator(s). + inferred 1 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd". +INFO:Xst:1799 - State write_a is never reached in FSM . +INFO:Xst:1799 - State read_a is never reached in FSM . +INFO:Xst:1799 - State burst_stop is never reached in FSM . +INFO:Xst:1799 - State self_ref is never reached in FSM . +INFO:Xst:1799 - State pre_pwr_down is never reached in FSM . +INFO:Xst:1799 - State act_pwr_down is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 8 | + | Transitions | 28 | + | Inputs | 10 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | asynchronous | + | Reset State | pwr_down | + | Power Up State | pwr_down | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 10x4-bit ROM for signal <$mux0000> created at line 98. + Found 2-bit register for signal . + Found 2-bit subtractor for signal created at line 281. + Found 1-bit register for signal . + Found 4-bit down counter for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 ROM(s). + inferred 1 Counter(s). + inferred 4 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 32x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 32 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Clock enable | ce (positive) | + | Reset | rst (positive) | + | Reset type | asynchronous | + | Reset State | st_init | + | Power Up State | st_init | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 10-bit up counter for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 Counter(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_sync.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 5 | + | Transitions | 9 | + | Inputs | 4 | + | Outputs | 5 | + | Clock | clk (rising_edge) | + | Clock enable | ce (positive) | + | Reset | rst (positive) | + | Reset type | asynchronous | + | Reset State | st_init | + | Power Up State | st_init | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 10-bit up counter for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 Counter(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 2048x64-bit dual-port RAM for signal . + Found 64-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/gray_counter.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal created at line 80. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Found 1-bit xor2 for signal created at line 48. + Summary: + inferred 36 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit updown counter for signal . + Found 1-bit register for signal . + Found 10-bit comparator lessequal for signal created at line 108. + Found 10-bit comparator greatequal for signal created at line 94. + Found 1-bit register for signal . + Found 9-bit register for signal . + Found 9-bit adder for signal created at line 196. + Found 9-bit comparator equal for signal created at line 144. + Found 9-bit comparator equal for signal created at line 139. + Found 9-bit register for signal . + Found 9-bit adder for signal created at line 178. + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 23 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 512x64-bit dual-port RAM for signal . + Found 64-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 64 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 3-bit updown counter for signal . + Found 1-bit register for signal . + Found 3-bit comparator lessequal for signal created at line 108. + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 196. + Found 2-bit comparator equal for signal created at line 144. + Found 2-bit comparator equal for signal created at line 139. + Found 2-bit register for signal . + Found 2-bit adder for signal created at line 178. + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 8 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 3 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 4x105-bit dual-port RAM for signal . + Found 105-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 105 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd". + Found 4096x8-bit ROM for signal created at line 4378. + Found 8-bit register for signal . + Summary: + inferred 1 ROM(s). + inferred 8 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 4096x8-bit dual-port RAM for signal . + Found 8-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 8 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync_ctrl.vhd". +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 9-bit updown counter for signal . + Found 1-bit register for signal . + Found 9-bit comparator lessequal for signal created at line 108. + Found 9-bit comparator greatequal for signal created at line 94. + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 196. + Found 8-bit comparator equal for signal created at line 144. + Found 8-bit comparator equal for signal created at line 139. + Found 8-bit register for signal . + Found 8-bit adder for signal created at line 178. + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 21 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/dpram_1w1r.vhd". + Found 256x18-bit dual-port RAM for signal . + Found 18-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 18 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/singleshot.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 6 | + | Inputs | 1 | + | Outputs | 1 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Summary: + inferred 1 Finite State Machine(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/singleshot.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 6 | + | Inputs | 1 | + | Outputs | 1 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Summary: + inferred 1 Finite State Machine(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ps2_port/src/ps2_core.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +INFO:Xst:1799 - State tx_start_latency_st is never reached in FSM . +INFO:Xst:1799 - State tx_stop_sample_st is never reached in FSM . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 18 | + | Transitions | 41 | + | Inputs | 5 | + | Outputs | 30 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | tx_idle_st | + | Power Up State | tx_idle_st | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 14 | + | Transitions | 38 | + | Inputs | 6 | + | Outputs | 8 | + | Clock | clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | start_wait_st | + | Power Up State | start_wait_st | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 7-bit down counter for signal . + Found 3-bit down counter for signal . + Found 3-bit down counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 14-bit down counter for signal . + Found 14-bit down counter for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 2 Finite State Machine(s). + inferred 5 Counter(s). + inferred 44 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ps2_port/src/debounce.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 7 | + | Inputs | 3 | + | Outputs | 2 | + | Clock | clk (rising_edge) | + | Clock enable | rst (negative) | + | Power Up State | init_st | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit subtractor for signal created at line 59. + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 5 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/projects/mips_sys/src/clockgen_virtex4.vhd". + Found 1-bit register for signal . + Found 5-bit down counter for signal . + Found 20-bit register for signal . + Found 20-bit register for signal . + Found 20-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 61 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ps2_port/src/ps2_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 16-bit register for signal >. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 34 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ps2_port/src/ps2_phy_virtex.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/projects/mips_sys/src/bootloader.ROM_ld.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 2048x32-bit dual-port RAM for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 48-bit register for signal . + Found 48-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 160 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/kcuart_tx.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/bbfifo_16x8.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/kcuart_rx.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit adder for signal . + Found 6-bit subtractor for signal created at line 192. + Found 6-bit register for signal . + Found 6-bit adder for signal . + Found 6-bit subtractor for signal created at line 212. + Found 1-bit register for signal . + Found 6-bit comparator lessequal for signal created at line 207. + Found 6-bit comparator greatequal for signal created at line 187. + Found 1-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit register for signal . + Found 6-bit comparator equal for signal created at line 147. + Found 6-bit comparator equal for signal created at line 137. + Summary: + inferred 88 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd". + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit tristate buffer for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 4-bit register for signal . + Found 32-bit tristate buffer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 64-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 2-bit register for signal

. + Found 4-bit register for signal . + Found 13-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 244 D-type flip-flop(s). + inferred 36 Tristate(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/char_gen.vhd". + Found 32x12-bit ROM for signal created at line 99. + Found 32x8-bit ROM for signal created at line 451. + Found 32x12-bit ROM for signal created at line 99. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 8 | + | Inputs | 4 | + | Outputs | 5 | + | Clock | sys_clk (rising_edge) | + | Reset | rst (positive) | + | Reset type | synchronous | + | Reset State | cg_init | + | Power Up State | cg_init | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 12-bit adder for signal . + Found 12-bit adder for signal created at line 267. + Found 12-bit adder for signal created at line 245. + Found 12-bit up counter for signal . + Found 12-bit comparator greatequal for signal created at line 304. + Found 8-bit register for signal . + Found 8-bit comparator less for signal created at line 330. + Found 8-bit subtractor for signal created at line 338. + Found 1-bit register for signal . + Found 7-bit up counter for signal . + Found 7-bit comparator greatequal for signal created at line 518. + Found 5-bit register for signal . + Found 5-bit adder for signal created at line 527. + Found 5-bit comparator greatequal for signal created at line 526. + Found 4-bit comparator greatequal for signal created at line 522. + Found 3-bit comparator greatequal for signal created at line 514. + Found 5-bit comparator less for signal created at line 526. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 1-bit xor2 for signal created at line 473. + Found 4-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 515. + Found 3-bit comparator less for signal created at line 514. + Found 4-bit up counter for signal . + Found 4-bit comparator less for signal created at line 522. + Found 7-bit comparator less for signal created at line 518. + Found 7-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 7-bit comparator less for signal created at line 356. + Found 7-bit up counter for signal . + Found 7-bit comparator greatequal for signal created at line 356. + Found 7-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 8-bit comparator greatequal for signal created at line 330. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit comparator less for signal created at line 376. + Found 5-bit up counter for signal . + Found 5-bit comparator greatequal for signal created at line 376. + Found 5-bit register for signal . + Found 5-bit up counter for signal . + Found 8-bit register for signal . + Found 7-bit comparator equal for signal created at line 450. + Found 5-bit comparator equal for signal created at line 450. + Found 1-bit register for signal . + Found 5-bit comparator less for signal created at line 436. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit adder for signal created at line 532. + Found 5-bit comparator less for signal created at line 531. + Found 7-bit register for signal . + Found 5-bit register for signal . + Found 7-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 5-bit adder for signal created at line 399. + Summary: + inferred 1 Finite State Machine(s). + inferred 3 ROM(s). + inferred 6 Counter(s). + inferred 116 D-type flip-flop(s). + inferred 8 Adder/Subtractor(s). + inferred 19 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_timing.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async_ctrl.vhd". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal created at line 192. + Found 12-bit register for signal . + Found 12-bit adder for signal . + Found 12-bit subtractor for signal created at line 212. + Found 1-bit register for signal . + Found 12-bit comparator lessequal for signal created at line 207. + Found 12-bit comparator greatequal for signal created at line 187. + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 12-bit comparator equal for signal created at line 147. + Found 12-bit comparator equal for signal created at line 137. + Summary: + inferred 172 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 4 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_sync.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_in.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 9 | + | Inputs | 5 | + | Outputs | 3 | + | Clock | ac_bit_clk (rising_edge) | + | Reset | ac_reset (positive) | + | Reset type | asynchronous | + | Reset State | ac_idle | + | Power Up State | ac_idle | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 13-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 20-bit register for signal . + Found 5-bit up counter for signal . + Found 240-bit register for signal . + Found 4-bit comparator greater for signal created at line 127. + Found 20-bit register for signal . + Found 4-bit up counter for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 2 Counter(s). + inferred 331 D-type flip-flop(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_out.vhd". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 6 | + | Inputs | 3 | + | Outputs | 3 | + | Clock | ac_bit_clk (rising_edge) | + | Reset | ac_reset (positive) | + | Reset type | asynchronous | + | Reset State | ac_idle | + | Power Up State | ac_idle | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 5-bit up counter for signal . + Found 240-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 4-bit up counter for signal . + Found 20-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 2 Counter(s). + inferred 275 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/misc/rom_wb.vhd". + Found 1-bit register for signal . + Summary: + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/uart_tx.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/uart_rx.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_backend.vhd". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input <3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input <3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 29 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/FIFO/src/fifo_async.vhd". +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac_io.vhd". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit down counter for signal . + Found 10-bit subtractor for signal created at line 165. + Found 1-bit register for signal >. + Summary: + inferred 1 Counter(s). + inferred 3 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/uart/uart_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 16-bit register for signal >. + Found 1-bit register for signal . + Found 16-bit up counter for signal . + Found 16-bit comparator equal for signal created at line 146. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 48 D-type flip-flop(s). + inferred 1 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/VGA_ctrl/src/vga_frontend64.vhd". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:653 - Signal is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 8 | + | Transitions | 22 | + | Inputs | 10 | + | Outputs | 9 | + | Clock | CLK_I (rising_edge) | + | Reset | RST_I (positive) | + | Reset type | synchronous | + | Reset State | init | + | Power Up State | init | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit adder for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 9-bit down counter for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 639. + Found 32-bit comparator equal for signal created at line 638. + Found 32-bit comparator not equal for signal created at line 638. + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit comparator not equal for signal created at line 642. + Found 32-bit up accumulator for signal . + Found 32-bit comparator equal for signal created at line 642. + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 640. + Found 4-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 609. + Found 32-bit comparator equal for signal created at line 608. + Found 32-bit comparator not equal for signal created at line 608. + Found 32-bit up counter for signal . + Found 1-bit register for signal . + Found 32-bit comparator not equal for signal created at line 612. + Found 32-bit up accumulator for signal . + Found 32-bit comparator equal for signal created at line 612. + Found 32-bit register for signal . + Found 32-bit adder for signal created at line 610. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 29-bit comparator equal for signal created at line 549. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 18-bit up counter for signal . + Found 29-bit up counter for signal . + Found 29-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 6 Counter(s). + inferred 2 Accumulator(s). + inferred 677 D-type flip-flop(s). + inferred 7 Adder/Subtractor(s). + inferred 9 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/ac97_ctrl/src/core/ac97_wb.vhd". +WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:1780 - Signal is never used or assigned. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Found 32-bit register for signal . + Found 1-bit register for signal . + Found 20-bit register for signal . + Found 20-bit register for signal . + Found 1-bit register for signal . + Found 4-bit up counter for signal . + Found 32-bit register for signal . + Found 32-bit 4-to-1 multiplexer for signal created at line 296. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 32-bit 4-to-1 multiplexer for signal created at line 296. + Found 32-bit register for signal . + Found 32-bit 4-to-1 multiplexer for signal created at line 296. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Counter(s). + inferred 168 D-type flip-flop(s). + inferred 96 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +Unit synthesized. + + +Synthesizing Unit . + Related source file is "W:/vhdl/projects/mips_sys/src/mips_sys.vhd". +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000. +WARNING:Xst:653 - Signal > is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000000000000000. +WARNING:Xst:646 - Signal > is assigned but never used. This unconnected signal will be trimmed during the optimization process. + Using one-hot encoding for signal . + Found 32-bit 4-to-1 multiplexer for signal . + Found 2-bit register for signal . + Found 1-bit register for signal >. + Found 6-bit register for signal . + Found 64-bit 4-to-1 multiplexer for signal . + Summary: + inferred 9 D-type flip-flop(s). + inferred 96 Multiplexer(s). +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 10 + 2048x32-bit dual-port RAM : 1 + 2048x64-bit dual-port RAM : 1 + 256x18-bit dual-port RAM : 1 + 32x30-bit dual-port RAM : 1 + 32x32-bit dual-port RAM : 1 + 32x64-bit dual-port RAM : 1 + 32x72-bit dual-port RAM : 1 + 4096x8-bit dual-port RAM : 1 + 4x105-bit dual-port RAM : 1 + 512x64-bit dual-port RAM : 1 +# ROMs : 6 + 10x4-bit ROM : 1 + 15x27-bit ROM : 1 + 32x12-bit ROM : 2 + 32x8-bit ROM : 1 + 4096x8-bit ROM : 1 +# Adders/Subtractors : 53 + 10-bit subtractor : 1 + 12-bit adder : 7 + 12-bit subtractor : 2 + 2-bit adder : 2 + 2-bit subtractor : 1 + 3-bit adder : 1 + 3-bit subtractor : 4 + 32-bit adder : 7 + 5-bit adder : 5 + 6-bit adder : 12 + 6-bit subtractor : 6 + 8-bit adder : 2 + 8-bit subtractor : 1 + 9-bit adder : 2 +# Counters : 49 + 10-bit down counter : 2 + 10-bit up counter : 2 + 10-bit updown counter : 1 + 12-bit up counter : 1 + 14-bit down counter : 4 + 15-bit down counter : 1 + 16-bit up counter : 2 + 18-bit up counter : 1 + 29-bit up counter : 2 + 3-bit down counter : 4 + 3-bit updown counter : 1 + 32-bit up counter : 6 + 4-bit down counter : 3 + 4-bit up counter : 4 + 5-bit down counter : 1 + 5-bit up counter : 5 + 6-bit updown counter : 1 + 7-bit down counter : 2 + 7-bit up counter : 3 + 8-bit down counter : 1 + 9-bit down counter : 1 + 9-bit updown counter : 1 +# Accumulators : 2 + 32-bit up loadable accumulator : 2 +# Registers : 739 + 1-bit register : 493 + 105-bit register : 1 + 12-bit register : 20 + 13-bit register : 5 + 16-bit register : 6 + 18-bit register : 1 + 2-bit register : 10 + 20-bit register : 33 + 25-bit register : 2 + 3-bit register : 5 + 30-bit register : 1 + 32-bit register : 34 + 4-bit register : 15 + 48-bit register : 2 + 5-bit register : 9 + 6-bit register : 61 + 64-bit register : 5 + 7-bit register : 4 + 72-bit register : 1 + 8-bit register : 28 + 9-bit register : 3 +# Comparators : 71 + 10-bit comparator greatequal : 1 + 10-bit comparator lessequal : 1 + 12-bit comparator equal : 2 + 12-bit comparator greatequal : 2 + 12-bit comparator lessequal : 1 + 13-bit comparator not equal : 1 + 16-bit comparator equal : 2 + 2-bit comparator equal : 2 + 21-bit comparator equal : 1 + 29-bit comparator equal : 1 + 3-bit comparator greatequal : 1 + 3-bit comparator less : 1 + 3-bit comparator lessequal : 1 + 32-bit comparator equal : 4 + 32-bit comparator greatequal : 3 + 32-bit comparator less : 3 + 32-bit comparator not equal : 4 + 4-bit comparator greatequal : 1 + 4-bit comparator greater : 1 + 4-bit comparator less : 1 + 5-bit comparator equal : 3 + 5-bit comparator greatequal : 2 + 5-bit comparator less : 4 + 6-bit comparator equal : 6 + 6-bit comparator greatequal : 4 + 6-bit comparator lessequal : 4 + 7-bit comparator equal : 1 + 7-bit comparator greatequal : 3 + 7-bit comparator less : 2 + 8-bit comparator equal : 2 + 8-bit comparator greatequal : 1 + 8-bit comparator less : 1 + 9-bit comparator equal : 2 + 9-bit comparator greatequal : 1 + 9-bit comparator lessequal : 1 +# Multiplexers : 6 + 1-bit 4-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 4 + 64-bit 4-to-1 multiplexer : 1 +# Tristates : 39 + 1-bit tristate buffer : 36 + 16-bit tristate buffer : 1 + 32-bit tristate buffer : 1 + 4-bit tristate buffer : 1 +# Xors : 60 + 1-bit xor2 : 60 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +---------------------------------- + State | Encoding +---------------------------------- + init | 00000001 + rdy | 00000010 + scan_bus_request | 00000100 + scan_bus_read | 00100000 + blit_src_bus_request | 00001000 + blit_src_bus_read | 01000000 + blit_dst_bus_request | 00010000 + blit_dst_bus_fin | 10000000 +---------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +--------------------- + State | Encoding +--------------------- + ac_idle | 00 + ac_tag | 01 + ac_data | 10 +--------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +--------------------- + State | Encoding +--------------------- + ac_idle | 00 + ac_tag | 01 + ac_data | 10 +--------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +--------------------------- + State | Encoding +--------------------------- + cg_init | 00 + cg_ready | 10 + cg_clr_line | 11 + cg_clr_screen | 01 +--------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +------------------------------ + State | Encoding +------------------------------ + start_wait_st | 0000 + start_trans_st | 0001 + start_sample_st | 0011 + data_wait_st | 0010 + data_trans_st | 0110 + data_sample_st | 0111 + parity_wait_st | 0101 + parity_trans_st | 0100 + parity_sample_st | 1100 + stop_wait_st | 1111 + stop_trans_st | 1110 + stop_sample_st | 1010 + valid_st | 1011 + abort_st | 1101 +------------------------------ +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------------------------- + State | Encoding +------------------------------------------- + tx_idle_st | 000000000000000001 + tx_clock_assert_st | 000000000000000010 + tx_start_latency_st | unreached + tx_start_assert_st | 000000000000000100 + tx_clock_release_st | 000000000000001000 + tx_dev_trans_st | 000000000000100000 + tx_data_wait_st | 000000000001000000 + tx_data_trans_st | 000000001000000000 + tx_data_sample_st | 000000000010000000 + tx_parity_update_st | 000000000100000000 + tx_dev_wait_st | 000000000000010000 + tx_parity_wait_st | 000000100000000000 + tx_parity_trans_st | 000000010000000000 + tx_parity_sample_st | 000001000000000000 + tx_stop_wait_st | 000100000000000000 + tx_stop_trans_st | 000010000000000000 + tx_stop_sample_st | unreached + tx_ack_trans_st | 001000000000000000 + tx_ack_sample_st | 010000000000000000 + tx_valid_st | 100000000000000000 +------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +---------------------- + State | Encoding +---------------------- + idle | 00 + shot_in | 01 + active | 11 + shot_out | 10 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +---------------------- + State | Encoding +---------------------- + idle | 00 + shot_in | 01 + active | 11 + shot_out | 10 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +---------------------- + State | Encoding +---------------------- + st_init | 000 + st_scan | 100 + st_front | 001 + st_sync | 010 + st_back | 011 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +---------------------- + State | Encoding +---------------------- + st_init | 000 + st_scan | 100 + st_front | 001 + st_sync | 010 + st_back | 011 +---------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +-------------------------- + State | Encoding +-------------------------- + pwr_down | 00000001 + precharge | 00000100 + mode | 00001000 + idle | 00000010 + row_act | 00010000 + write | 10000000 + write_a | unreached + read | 01000000 + read_a | unreached + burst_stop | unreached + self_ref | unreached + auto_ref | 00100000 + pre_pwr_down | unreached + act_pwr_down | unreached +-------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +--------------------------------- + State | Encoding +--------------------------------- + reset | 0000000000001 + power_wait | 0000000000010 + init | 0000000000100 + init_wait | 0000000010000 + user_ready | 0000000001000 + user_write_pre | 0000001000000 + user_write_act | 0000010000000 + user_write | 0000100000000 + user_read_pre | 0001000000000 + user_read_act | 0010000000000 + user_read | 0100000000000 + refresh_pre | 0000000100000 + refresh | 1000000000000 +--------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +--------------------- + State | Encoding +--------------------- + start | 000 + reset | 001 + idle | 011 + leadin | 010 + pulse | 110 + leadout | 111 + release | 101 +--------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +--------------------- + State | Encoding +--------------------- + start | 000 + reset | 001 + idle | 010 + leadin | 011 + pulse | 100 + leadout | 101 + release | 110 +--------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +--------------------- + State | Encoding +--------------------- + init_st | 00 + wait_st | 01 + rel_st | 11 +--------------------- +Loading device for application Rf_Device from file '4vsx35.nph' in environment C:\Programme\Xilinx101\ISE. +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . +WARNING:Xst:2404 - FFs/Latches > (without init value) have a constant value of 0 in block . + +Synthesizing (advanced) Unit . +INFO:Xst - In order to maximize performance and save block RAM resources, the small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style. +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The ROM will be implemented as a read-only BLOCK RAM, absorbing the register: . +INFO:Xst - The RAM will be implemented as BLOCK RAM + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4096-word x 8-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to internal node | high | + | addrA | connected to signal | | + | diA | connected to internal node | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 32-word x 30-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 32-word x 30-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 32-word x 72-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 32-word x 72-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 32-word x 64-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 32-word x 64-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 64-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 64-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 512-word x 64-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 512-word x 64-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4-word x 105-bit | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 4-word x 105-bit | | + | addrB | connected to signal | | + | doB | connected to internal node | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 4096-word x 8-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 4096-word x 8-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 256-word x 18-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 256-word x 18-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 32-word x 32-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 32-word x 32-bit | | + | mode | read-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +INFO:Xst - The RAM will be implemented as a BLOCK RAM, absorbing the following register(s): + ----------------------------------------------------------------------- + | ram_type | Block | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2048-word x 32-bit | | + | mode | no-change | | + | clkA | connected to signal | rise | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2048-word x 32-bit | | + | mode | write-first | | + | clkB | connected to signal | rise | + | enB | connected to signal | high | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + | optimization | speed | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 31 FFs/Latches, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 3 FFs/Latches, which will be removed : +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 11 + 2048x32-bit dual-port block RAM : 1 + 2048x64-bit dual-port block RAM : 1 + 256x18-bit dual-port block RAM : 1 + 32x30-bit dual-port block RAM : 1 + 32x32-bit dual-port block RAM : 1 + 32x64-bit dual-port block RAM : 1 + 32x72-bit dual-port block RAM : 1 + 4096x8-bit dual-port block RAM : 1 + 4096x8-bit single-port block RAM : 1 + 4x105-bit dual-port distributed RAM : 1 + 512x64-bit dual-port block RAM : 1 +# ROMs : 5 + 10x4-bit ROM : 1 + 15x27-bit ROM : 1 + 32x12-bit ROM : 2 + 32x8-bit ROM : 1 +# Adders/Subtractors : 53 + 10-bit subtractor : 1 + 12-bit adder : 7 + 12-bit subtractor : 2 + 2-bit adder : 2 + 2-bit subtractor : 1 + 3-bit adder : 1 + 3-bit subtractor : 4 + 32-bit adder : 7 + 5-bit adder : 5 + 6-bit adder : 12 + 6-bit subtractor : 6 + 8-bit adder : 2 + 8-bit subtractor : 1 + 9-bit adder : 2 +# Counters : 49 + 10-bit down counter : 2 + 10-bit up counter : 2 + 10-bit updown counter : 1 + 12-bit up counter : 1 + 14-bit down counter : 4 + 15-bit down counter : 1 + 16-bit up counter : 2 + 18-bit up counter : 1 + 29-bit up counter : 2 + 3-bit down counter : 4 + 3-bit updown counter : 1 + 32-bit up counter : 6 + 4-bit down counter : 3 + 4-bit up counter : 4 + 5-bit down counter : 1 + 5-bit up counter : 5 + 6-bit updown counter : 1 + 7-bit down counter : 2 + 7-bit up counter : 3 + 8-bit down counter : 1 + 9-bit down counter : 1 + 9-bit updown counter : 1 +# Accumulators : 2 + 32-bit up loadable accumulator : 2 +# Registers : 3649 + Flip-Flops : 3649 +# Comparators : 71 + 10-bit comparator greatequal : 1 + 10-bit comparator lessequal : 1 + 12-bit comparator equal : 2 + 12-bit comparator greatequal : 2 + 12-bit comparator lessequal : 1 + 13-bit comparator not equal : 1 + 16-bit comparator equal : 2 + 2-bit comparator equal : 2 + 21-bit comparator equal : 1 + 29-bit comparator equal : 1 + 3-bit comparator greatequal : 1 + 3-bit comparator less : 1 + 3-bit comparator lessequal : 1 + 32-bit comparator equal : 4 + 32-bit comparator greatequal : 3 + 32-bit comparator less : 3 + 32-bit comparator not equal : 4 + 4-bit comparator greatequal : 1 + 4-bit comparator greater : 1 + 4-bit comparator less : 1 + 5-bit comparator equal : 3 + 5-bit comparator greatequal : 2 + 5-bit comparator less : 4 + 6-bit comparator equal : 6 + 6-bit comparator greatequal : 4 + 6-bit comparator lessequal : 4 + 7-bit comparator equal : 1 + 7-bit comparator greatequal : 3 + 7-bit comparator less : 2 + 8-bit comparator equal : 2 + 8-bit comparator greatequal : 1 + 8-bit comparator less : 1 + 9-bit comparator equal : 2 + 9-bit comparator greatequal : 1 + 9-bit comparator lessequal : 1 +# Multiplexers : 6 + 1-bit 4-to-1 multiplexer : 1 + 32-bit 4-to-1 multiplexer : 4 + 64-bit 4-to-1 multiplexer : 1 +# Xors : 60 + 1-bit xor2 : 60 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 50 FFs/Latches, which will be removed : +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +INFO:Xst:1901 - Instance inst_DCM_VGA_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV +INFO:Xst:1901 - Instance inst_DCM_SYS_FX in unit clockgen of type DCM_BASE has been replaced by DCM_ADV +INFO:Xst:1901 - Instance inst_DCM_SDRCLK_0 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV +INFO:Xst:1901 - Instance inst_DCM_SDRCLK_1 in unit clockgen of type DCM_BASE has been replaced by DCM_ADV +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 7 FFs/Latches, which will be removed : + +Optimizing unit ... +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . + +Optimizing unit ... +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process. +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . +WARNING:Xst:2677 - Node of sequential type is unconnected in block . + +Mapping all equations... +WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch. +WARNING:Xst:2036 - Inserting OBUF on port > driven by black box . Possible simulation mismatch. +Building and optimizing final netlist ... +Changing polarity of register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +Found area constraint ratio of 100 (+ 5) on block mips_sys, actual ratio is 19. +Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/Mcount_count_cy<0> +Forward register balancing over carry chain inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/Mcount_count_cy<0> +Forward register balancing over carry chain inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/Madd_nxtb_addsub0000_cy<0> +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2260 - The FF/Latch in Unit is equivalent to the following FF/Latch : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following FF/Latch, which will be removed : + +Pipelining and Register Balancing Report ... + +Processing Unit : + Register(s) inst_vga_frontend/s_FSM_FFd4 inst_vga_frontend/s_FSM_FFd1 has(ve) been forward balanced into : inst_vga_frontend/s_FSM_Out51_FRB. + Register(s) inst_ac97_wb/ac_cmd_addr_19 has(ve) been backward balanced into : inst_ac97_wb/ac_cmd_addr_19_BRB0. + Register(s) inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19 has(ve) been backward balanced into : inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB1. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_1_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_2_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_3_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_7_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_8_BRB2 . + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cas_n_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB2 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.cs_n_BRB3. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.ras_n_BRB1. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cmd.we_n_BRB1. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt_2_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p1_2_BRB2. + Register(s) inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2 has(ve) been backward balanced into : inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB0 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB1 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/p2_2_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_1_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_10_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_11_BRB1. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_2_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_3_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_4_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_5_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_6_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_7_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_8_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff0_9_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_10_BRB2. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB0 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_11_BRB1. + Register(s) inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9 has(ve) been backward balanced into : inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB1 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_9_BRB2. + Register(s) inst_vga_frontend/inst_vga_backend/hsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/hsync_r_BRB0 inst_vga_frontend/inst_vga_backend/hsync_r_BRB1. + Register(s) inst_vga_frontend/inst_vga_backend/vsync_r has(ve) been backward balanced into : inst_vga_frontend/inst_vga_backend/vsync_r_BRB0. +Unit processed. +Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute +Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute +Replicating register inst_ps2_wb_1/inst_ps2_core/ps2_data_tx to handle IOB=TRUE attribute +Replicating register inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx to handle IOB=TRUE attribute +Replicating register inst_ac97_wb/inst_ac_io/inst_ac_out/ac_ssync to handle IOB=TRUE attribute +Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10 to handle IOB=TRUE attribute +Replicating register inst_usb_port/Mtrien_async_d to handle IOB=TRUE attribute +Replicating register inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0 to handle IOB=TRUE attribute +Replicating register inst_flash_port/Mtrien_async_d to handle IOB=TRUE attribute + +FlipFlop arb_gnt_0 has been replicated 1 time(s) +FlipFlop arb_gnt_1 has been replicated 1 time(s) +FlipFlop inst_clockgen/sys_rst_out has been replicated 11 time(s) +FlipFlop inst_vga_frontend/s_FSM_FFd2 has been replicated 1 time(s) +FlipFlop inst_vga_frontend/s_FSM_FFd5 has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 4-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 20-bit shift register for signal . + Found 20-bit shift register for signal . + Found 20-bit shift register for signal . + Found 6-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 3-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . + Found 2-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 3545 + Flip-Flops : 3545 +# Shift Registers : 101 + 2-bit shift register : 3 + 20-bit shift register : 3 + 3-bit shift register : 93 + 4-bit shift register : 1 + 6-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : mips_sys.ngr +Top Level Output File Name : mips_sys +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 226 + +Cell Usage : +# BELS : 6441 +# GND : 1 +# INV : 95 +# LUT1 : 352 +# LUT2 : 532 +# LUT2_D : 2 +# LUT2_L : 2 +# LUT3 : 1039 +# LUT3_D : 14 +# LUT3_L : 6 +# LUT4 : 2181 +# LUT4_D : 32 +# LUT4_L : 48 +# MULT_AND : 6 +# MUXCY : 1017 +# MUXF5 : 278 +# MUXF6 : 2 +# VCC : 1 +# XORCY : 833 +# FlipFlops/Latches : 3786 +# FD : 314 +# FD_1 : 85 +# FDC : 268 +# FDC_1 : 20 +# FDCE : 255 +# FDCPE : 4 +# FDE : 1370 +# FDP : 78 +# FDPE : 18 +# FDR : 191 +# FDR_1 : 1 +# FDRE : 936 +# FDRS : 58 +# FDRSE : 6 +# FDS : 24 +# FDSE : 84 +# IDDR : 32 +# ODDR : 42 +# RAMS : 127 +# RAM16X1D : 103 +# RAMB16 : 24 +# Shift Registers : 176 +# SRL16 : 100 +# SRL16E : 73 +# SRLC16 : 3 +# Clock Buffers : 12 +# BUFG : 12 +# IO Buffers : 226 +# IBUF : 21 +# IBUFG : 2 +# IOBUF : 84 +# OBUF : 111 +# OBUFT : 8 +# DCM_ADVs : 4 +# DCM_ADV : 4 +# Others : 2 +# BSCAN_VIRTEX4 : 1 +# mips_top : 1 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 4vsx35ff668-10 + + Number of Slices: 2803 out of 15360 18% + Number of Slice Flip Flops: 3501 out of 30720 11% + Number of 4 input LUTs: 4685 out of 30720 15% + Number used as logic: 4303 + Number used as Shift registers: 176 + Number used as RAMs: 206 + Number of IOs: 226 + Number of bonded IOBs: 226 out of 448 50% + IOB Flip Flops: 285 + Number of FIFO16/RAMB16s: 24 out of 192 12% + Number used as RAMB16s: 24 + Number of GCLKs: 12 out of 32 37% + Number of DCM_ADVs: 4 out of 8 50% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+---------------------------------------------------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+---------------------------------------------------------------------------+-------+ +sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX | 3379 | +sys_clk_in | inst_clockgen/inst_DCM_SYS_FX:CLKFX+inst_clockgen/inst_DCM_SDRCLK_0:CLK270| 68 | +inst_rom_wb/inst_rom/bs_clk0 | BUFG | 98 | +sys_clk_in | inst_clockgen/inst_DCM_VGA_FX:CLKFX | 252 | +sys_ac97_bit_clk | IBUF+BUFG | 269 | +sys_sdr_clk_fb | inst_clockgen/inst_DCM_SDRCLK_1:CLK270 | 32 | +inst_rom_wb/inst_rom/bs_update0 | BUFG | 4 | +-----------------------------------+---------------------------------------------------------------------------+-------+ + +Asynchronous Control Signals Information: +---------------------------------------- +-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ +RST_O_4(inst_clockgen/sys_rst_out_10:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt_3)| 289 | +inst_rom_wb/inst_rom/bs_rst(inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:RESET) | NONE(inst_rom_wb/inst_rom/user_rego_15) | 96 | +RST_O(inst_clockgen/sys_rst_out:Q) | NONE(inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w/gcnt_2) | 75 | +inst_ac97_wb/inst_ac_io/ac_reset(inst_ac97_wb/inst_ac_io/ac_reset:Q) | NONE(inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_19_BRB0) | 52 | +inst_ac97_wb/tx_fifo_rst(inst_ac97_wb/tx_fifo_rst1:O) | NONE(inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl/pR_0) | 29 | +inst_vga_frontend/blit_reset(inst_vga_frontend/blit_reset1:O) | NONE(inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl/pR_4) | 21 | +inst_clockgen/sdr0_lock_inv(inst_clockgen/sdr0_lock_inv1_INV_0:O) | NONE(inst_clockgen/reset_pipe2_192) | 20 | +inst_clockgen/vga_fx_lock_inv(inst_clockgen/vga_fx_lock_inv1_INV_0:O) | NONE(inst_clockgen/vga_fx_lock_inv_shift12) | 20 | +rst_in(rst_in1:O) | NONE(inst_clockgen/reset_pipe0_192) | 20 | +inst_clockgen/sys_rst_out_or0000(inst_clockgen/sys_rst_out_or0000:O) | NONE(inst_clockgen/sys_rst_out_3) | 17 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0000(inst_ps2_phy_0/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_clk/output_and0001(inst_ps2_phy_0/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_0/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0000(inst_ps2_phy_0/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_0/Inst_debounce_data/output_and0001(inst_ps2_phy_0/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_0/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0000(inst_ps2_phy_1/Inst_debounce_clk/output_and00001:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_clk/output_and0001(inst_ps2_phy_1/Inst_debounce_clk/output_and00011:O) | NONE(inst_ps2_phy_1/Inst_debounce_clk/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0000(inst_ps2_phy_1/Inst_debounce_data/output_and00001:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +inst_ps2_phy_1/Inst_debounce_data/output_and0001(inst_ps2_phy_1/Inst_debounce_data/output_and00011:O)| NONE(inst_ps2_phy_1/Inst_debounce_data/input_last) | 1 | +-----------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -10 + + Minimum period: 10.566ns (Maximum Frequency: 94.648MHz) + Minimum input arrival time before clock: 8.065ns + Maximum output required time after clock: 10.235ns + Maximum combinational path delay: 9.843ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys_clk_in' + Clock period: 10.566ns (frequency: 94.648MHz) + Total number of paths / destination ports: 297831 / 8689 +------------------------------------------------------------------------- +Delay: 5.283ns (Levels of Logic = 10) + Source: inst_clockgen/sys_rst_out_1 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 (RAM) + Source Clock: sys_clk_in rising + Destination Clock: sys_clk_in rising 0.4X + + Data Path: inst_clockgen/sys_rst_out_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDPE:C->Q 5 0.360 0.546 inst_clockgen/sys_rst_out_1 (RST_O_0) + LUT4:I3->O 10 0.195 0.713 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 (inst_vga_frontend/inst_linefifo/ptr_r<0>) + LUT3:I1->O 2 0.195 0.602 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0>) + LUT4:I2->O 1 0.195 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0>) + MUXCY:S->O 1 0.366 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0>) + MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1>) + MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2>) + MUXCY:CI->O 1 0.045 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3>) + MUXCY:CI->O 1 0.044 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> (inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4>) + MUXCY:CI->O 2 0.263 0.377 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> (inst_vga_frontend/inst_linefifo/pre_empty) + INV:I->O 7 0.358 0.416 inst_vga_frontend/inst_linefifo/mem_rd_en1_INV_0 (inst_vga_frontend/inst_linefifo/mem_rd_en) + RAMB16:ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM7 + ---------------------------------------- + Total 5.283ns (2.629ns logic, 2.654ns route) + (49.8% logic, 50.2% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'inst_rom_wb/inst_rom/bs_clk0' + Clock period: 2.225ns (frequency: 449.438MHz) + Total number of paths / destination ports: 97 / 96 +------------------------------------------------------------------------- +Delay: 2.225ns (Levels of Logic = 0) + Source: inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF) + Destination: inst_rom_wb/inst_rom/user_regi_42 (FF) + Source Clock: inst_rom_wb/inst_rom/bs_clk0 rising + Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising + + Data Path: inst_rom_wb/inst_rom/Mshreg_user_regi_42 to inst_rom_wb/inst_rom/user_regi_42 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + SRL16E:CLK->Q 1 2.203 0.000 inst_rom_wb/inst_rom/Mshreg_user_regi_42 (inst_rom_wb/inst_rom/Mshreg_user_regi_42) + FDE:D 0.022 inst_rom_wb/inst_rom/user_regi_42 + ---------------------------------------- + Total 2.225ns (2.225ns logic, 0.000ns route) + (100.0% logic, 0.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'sys_ac97_bit_clk' + Clock period: 5.921ns (frequency: 168.893MHz) + Total number of paths / destination ports: 3602 / 516 +------------------------------------------------------------------------- +Delay: 5.921ns (Levels of Logic = 6) + Source: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 (FF) + Source Clock: sys_ac97_bit_clk rising + Destination Clock: sys_ac97_bit_clk rising + + Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 to inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_11 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 57 0.360 1.354 inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2 (inst_ac97_wb/inst_ac_io/inst_ac_out/slotcnt_2) + LUT3:I0->O 25 0.195 1.228 inst_ac97_wb/inst_ac_io/inst_ac_out/varindex0000_cmp_eq000211 (inst_ac97_wb/inst_ac_io/inst_ac_out/N27) + LUT4:I1->O 1 0.195 0.741 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>26) + LUT4:I0->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105_G (N1345) + MUXF5:I1->O 1 0.374 0.688 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>105) + LUT4:I1->O 1 0.195 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>1691 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169) + MUXF5:I1->O 1 0.374 0.000 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>169_f5 (inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_mux0000<9>) + FDCE:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_out/tx_reg_9 + ---------------------------------------- + Total 5.921ns (1.910ns logic, 4.011ns route) + (32.3% logic, 67.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_clk_in' + Total number of paths / destination ports: 43744 / 2286 +------------------------------------------------------------------------- +Offset: 8.065ns (Levels of Logic = 8) + Source: inst_mips_top:ADDR_O<29> (PAD) + Destination: inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 (FF) + Destination Clock: sys_clk_in rising + + Data Path: inst_mips_top:ADDR_O<29> to inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + mips_top:ADDR_O<29> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<29>) + LUT4_D:I0->O 3 0.195 0.756 Mmux_ADDR_O221 (ADDR_O<29>) + LUT4_D:I0->LO 1 0.195 0.225 CYC_I_flash_SW0 (N1530) + LUT4:I2->O 39 0.195 1.283 CYC_I_flash (CYC_I_flash) + LUT4:I1->O 1 0.195 0.523 SRDY_I26 (SRDY_I26) + LUT4_D:I3->LO 1 0.195 0.163 SRDY_I36 (N1542) + LUT3:I2->O 5 0.195 0.546 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read1 (inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/read) + LUT4_D:I3->O 1 0.195 0.523 inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl/pre_empty_and0000_SW0 (N392) + LUT3:I2->O 103 0.195 1.205 inst_vga_frontend/inst_bus_fifo/mem_rd_en1 (inst_vga_frontend/inst_bus_fifo/mem_rd_en) + FDE:CE 0.540 inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r/dout_b_2 + ---------------------------------------- + Total 8.065ns (2.100ns logic, 5.965ns route) + (26.0% logic, 74.0% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_clk0' + Total number of paths / destination ports: 99 / 99 +------------------------------------------------------------------------- +Offset: 2.301ns (Levels of Logic = 0) + Source: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT (PAD) + Destination: inst_rom_wb/inst_rom/Mshreg_user_regi_42 (FF) + Destination Clock: inst_rom_wb/inst_rom/bs_clk0 rising + + Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SHIFT to inst_rom_wb/inst_rom/Mshreg_user_regi_42 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BSCAN_VIRTEX4:SHIFT 98 0.000 1.186 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_shift) + SRL16E:CE 1.115 inst_rom_wb/inst_rom/Mshreg_user_regi_42 + ---------------------------------------- + Total 2.301ns (1.115ns logic, 1.186ns route) + (48.5% logic, 51.5% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_ac97_bit_clk' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 1.347ns (Levels of Logic = 1) + Source: sys_ac97_sdata_in (PAD) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0 (FF) + Destination Clock: sys_ac97_bit_clk falling + + Data Path: sys_ac97_sdata_in to inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.965 0.360 sys_ac97_sdata_in_IBUF (sys_ac97_sdata_in_IBUF) + FDC_1:D 0.022 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_0 + ---------------------------------------- + Total 1.347ns (0.987ns logic, 0.360ns route) + (73.3% logic, 26.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'sys_sdr_clk_fb' + Total number of paths / destination ports: 32 / 32 +------------------------------------------------------------------------- +Offset: 6.702ns (Levels of Logic = 1) + Source: sys_sdr_data<31> (PAD) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data (FF) + Destination Clock: sys_sdr_clk_fb rising +270 + + Data Path: sys_sdr_data<31> to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IOBUF:IO->O 1 0.965 0.360 sys_sdr_data_31_IOBUF (N398) + IDDR:D 5.377 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/gen_ddr_data_in[31].IDDR_data + ---------------------------------------- + Total 6.702ns (6.342ns logic, 0.360ns route) + (94.6% logic, 5.4% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'inst_rom_wb/inst_rom/bs_update0' + Total number of paths / destination ports: 16 / 16 +------------------------------------------------------------------------- +Offset: 1.341ns (Levels of Logic = 0) + Source: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL (PAD) + Destination: inst_rom_wb/inst_rom/Mram_word_array3 (RAM) + Destination Clock: inst_rom_wb/inst_rom/bs_update0 rising + + Data Path: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:SEL to inst_rom_wb/inst_rom/Mram_word_array3 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + BSCAN_VIRTEX4:SEL 16 0.000 0.593 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 (inst_rom_wb/inst_rom/bs_sel) + RAMB16:WEA0 0.748 inst_rom_wb/inst_rom/Mram_word_array3 + ---------------------------------------- + Total 1.341ns (0.748ns logic, 0.593ns route) + (55.8% logic, 44.2% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_clk_in' + Total number of paths / destination ports: 20341 / 226 +------------------------------------------------------------------------- +Offset: 10.235ns (Levels of Logic = 12) + Source: inst_vga_frontend/s_FSM_FFd2_1 (FF) + Destination: inst_mips_top:DAT_I<13> (PAD) + Source Clock: sys_clk_in rising + + Data Path: inst_vga_frontend/s_FSM_FFd2_1 to inst_mips_top:DAT_I<13> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRS:C->Q 1 0.360 0.585 inst_vga_frontend/s_FSM_FFd2_1 (inst_vga_frontend/s_FSM_FFd2_1) + LUT2:I0->O 1 0.195 0.523 inst_vga_frontend/s_FSM_Out61 (inst_vga_frontend/CYC_O_blit_src) + LUT4_D:I3->LO 1 0.195 0.163 inst_vga_frontend/CYC_O1 (N1535) + LUT4:I3->O 8 0.195 0.608 CYC_O1 (CYC_O) + LUT4_D:I3->O 17 0.195 0.961 CYC_I_ac971 (N55) + LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) + LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190) + LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) + LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886) + LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307) + LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858) + LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) + mips_top:DAT_I<13> 0.000 inst_mips_top + ---------------------------------------- + Total 10.235ns (2.700ns logic, 7.535ns route) + (26.4% logic, 73.6% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'sys_ac97_bit_clk' + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Offset: 4.677ns (Levels of Logic = 1) + Source: inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (FF) + Destination: sys_ac97_sdata_out (PAD) + Source Clock: sys_ac97_bit_clk rising + + Data Path: inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out to sys_ac97_sdata_out + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 1 0.360 0.360 inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out (inst_ac97_wb/inst_ac_io/inst_ac_out/ac_sdata_out) + OBUF:I->O 3.957 sys_ac97_sdata_out_OBUF (sys_ac97_sdata_out) + ---------------------------------------- + Total 4.677ns (4.317ns logic, 0.360ns route) + (92.3% logic, 7.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'inst_rom_wb/inst_rom/bs_clk0' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 0.720ns (Levels of Logic = 0) + Source: inst_rom_wb/inst_rom/user_rego_0 (FF) + Destination: inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO (PAD) + Source Clock: inst_rom_wb/inst_rom/bs_clk0 rising + + Data Path: inst_rom_wb/inst_rom/user_rego_0 to inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1:TDO + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 1 0.360 0.360 inst_rom_wb/inst_rom/user_rego_0 (inst_rom_wb/inst_rom/user_rego_0) + BSCAN_VIRTEX4:TDO 0.000 inst_rom_wb/inst_rom/BSCAN_VIRTEX4_inst1 + ---------------------------------------- + Total 0.720ns (0.360ns logic, 0.360ns route) + (50.0% logic, 50.0% route) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 5508 / 38 +------------------------------------------------------------------------- +Delay: 9.843ns (Levels of Logic = 11) + Source: inst_mips_top:ADDR_O<28> (PAD) + Destination: inst_mips_top:DAT_I<13> (PAD) + + Data Path: inst_mips_top:ADDR_O<28> to inst_mips_top:DAT_I<13> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + mips_top:ADDR_O<28> 1 0.000 0.741 inst_mips_top (ADDR_O_cpu<28>) + LUT4_D:I0->O 4 0.195 0.702 Mmux_ADDR_O211 (ADDR_O<28>) + LUT4:I1->O 3 0.195 0.600 CYC_I_ac971_SW0 (N390) + LUT4_D:I2->O 17 0.195 0.961 CYC_I_ac971 (N55) + LUT4_D:I0->O 48 0.195 1.371 CYC_I_ac972 (CYC_I_ac97) + LUT4:I0->O 1 0.195 0.523 MDAT_I<13>36_SW0 (N1190) + LUT4:I3->O 1 0.195 0.585 MDAT_I<13>36 (MDAT_I<13>36) + LUT4:I2->O 1 0.195 0.523 MDAT_I<13>84_SW0 (N886) + LUT4:I3->O 1 0.195 0.523 MDAT_I<13>84_SW1 (N1307) + LUT4:I3->O 1 0.195 0.585 MDAT_I<13>84 (MDAT_I<13>84) + LUT4:I2->O 1 0.195 0.585 MDAT_I<13>170_SW0 (N858) + LUT4:I2->O 0 0.195 0.000 MDAT_I<13>170 (MDAT_I<13>) + mips_top:DAT_I<13> 0.000 inst_mips_top + ---------------------------------------- + Total 9.843ns (2.145ns logic, 7.698ns route) + (21.8% logic, 78.2% route) + +========================================================================= + + +Total REAL time to Xst completion: 122.00 secs +Total CPU time to Xst completion: 122.11 secs + +--> + +Total memory usage is 337652 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 993 ( 0 filtered) +Number of infos : 143 ( 0 filtered) + diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.twr b/projects/mips_sys/ise101/mips_sys/mips_sys.twr new file mode 100644 index 0000000..800df48 --- /dev/null +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.twr @@ -0,0 +1,1443 @@ +-------------------------------------------------------------------------------- +Release 10.1.03 Trace (nt) +Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. + +C:\Programme\Xilinx101\ISE\bin\nt\unwrapped\trce.exe -ise +W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -v 3 -s 10 +-xml mips_sys mips_sys.ncd -o mips_sys.twr mips_sys.pcf -ucf +W:/vhdl/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf + +Design file: mips_sys.ncd +Physical constraint file: mips_sys.pcf +Device,package,speed: xc4vsx35,ff668,-10 (PRODUCTION 1.68 2008-07-25, STEPPING level ES) +Report level: verbose report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%; + + 3542 paths analyzed, 641 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 6.902ns. +-------------------------------------------------------------------------------- +Slack: 36.549ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 (FF) + Requirement: 40.000ns + Data Path Delay: 3.451ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns + Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y38.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 + SLICE_X29Y62.BY net (fanout=14) 2.873 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11> + SLICE_X29Y62.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 + ------------------------------------------------- --------------------------- + Total 3.451ns (0.578ns logic, 2.873ns route) + (16.7% logic, 83.3% route) + +-------------------------------------------------------------------------------- +Slack: 36.837ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 (FF) + Requirement: 40.000ns + Data Path Delay: 3.124ns (Levels of Logic = 0) + Clock Path Skew: -0.039ns (2.691 - 2.730) + Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns + Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X56Y28.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 + SLICE_X28Y62.BY net (fanout=13) 2.537 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10> + SLICE_X28Y62.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 + inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 + ------------------------------------------------- --------------------------- + Total 3.124ns (0.587ns logic, 2.537ns route) + (18.8% logic, 81.2% route) + +-------------------------------------------------------------------------------- +Slack: 36.841ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF) + Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF) + Requirement: 40.000ns + Data Path Delay: 2.936ns (Levels of Logic = 0) + Clock Path Skew: -0.223ns (2.568 - 2.791) + Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns + Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns + Clock Uncertainty: 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X66Y27.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<9> + inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 + SLICE_X50Y44.BY net (fanout=13) 2.349 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15> + SLICE_X50Y44.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15> + inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 + ------------------------------------------------- --------------------------- + Total 2.936ns (0.587ns logic, 2.349ns route) + (20.0% logic, 80.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%; + + 467886 paths analyzed, 11157 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 9.736ns. +-------------------------------------------------------------------------------- +Slack: 0.164ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/s_FSM_FFd5 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) + Requirement: 9.900ns + Data Path Delay: 9.627ns (Levels of Logic = 8) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 9.900ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 + inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> + inst_vga_frontend/blitfifo_color_we1_SW0 + SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 + SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O + inst_vga_frontend/blitfifo_color_we1 + SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 + SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> + inst_vga_frontend/inst_linefifo/mem_wr_en1 + SLICE_X55Y124.G1 net (fanout=41) 0.638 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc + SLICE_X55Y124.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<3>1 + SLICE_X56Y127.G2 net (fanout=3) 0.782 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<3> + SLICE_X56Y127.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> + SLICE_X56Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> + SLICE_X56Y128.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<4> + SLICE_X57Y128.F4 net (fanout=2) 0.396 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<4> + SLICE_X57Y128.YMUX Topy 0.777 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<4>1_INV_0 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> + SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> + SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + ------------------------------------------------- --------------------------- + Total 9.627ns (3.125ns logic, 6.502ns route) + (32.5% logic, 67.5% route) + +-------------------------------------------------------------------------------- +Slack: 0.202ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/s_FSM_FFd5 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) + Requirement: 9.900ns + Data Path Delay: 9.589ns (Levels of Logic = 9) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 9.900ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 + inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> + inst_vga_frontend/blitfifo_color_we1_SW0 + SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 + SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O + inst_vga_frontend/blitfifo_color_we1 + SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 + SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> + inst_vga_frontend/inst_linefifo/mem_wr_en1 + SLICE_X55Y122.F3 net (fanout=41) 0.258 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc + SLICE_X55Y122.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<0>1 + SLICE_X56Y126.F2 net (fanout=2) 0.758 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<0> + SLICE_X56Y126.COUT Topcyf 0.576 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X56Y127.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X56Y127.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> + SLICE_X57Y127.F3 net (fanout=2) 0.448 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> + SLICE_X57Y127.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X57Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X57Y128.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> + SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> + SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + ------------------------------------------------- --------------------------- + Total 9.589ns (3.439ns logic, 6.150ns route) + (35.9% logic, 64.1% route) + +-------------------------------------------------------------------------------- +Slack: 0.206ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/s_FSM_FFd5 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 (FF) + Requirement: 9.900ns + Data Path Delay: 9.585ns (Levels of Logic = 9) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 9.900ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/s_FSM_FFd5 to inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X39Y79.YQ Tcko 0.340 inst_vga_frontend/s_FSM_FFd5 + inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.F2 net (fanout=50) 1.789 inst_vga_frontend/s_FSM_FFd5 + SLICE_X48Y81.X Tilo 0.195 inst_rom_wb/inst_rom/user_rego<10> + inst_vga_frontend/blitfifo_color_we1_SW0 + SLICE_X49Y96.F3 net (fanout=1) 0.631 N374 + SLICE_X49Y96.X Tilo 0.194 inst_ac97_wb/ACK_O + inst_vga_frontend/blitfifo_color_we1 + SLICE_X55Y122.G4 net (fanout=18) 1.256 inst_vga_frontend/read_cnt_and0000 + SLICE_X55Y122.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/bcnt<0> + inst_vga_frontend/inst_linefifo/mem_wr_en1 + SLICE_X55Y123.G2 net (fanout=41) 0.365 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/winc + SLICE_X55Y123.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb_addsub0000<0>_FRB + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w/nxtb<1>1 + SLICE_X56Y126.G3 net (fanout=3) 0.662 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/bnxt_w<1> + SLICE_X56Y126.COUT Topcyg 0.561 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_lut<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X56Y127.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<1> + SLICE_X56Y127.XMUX Tcinx 0.435 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Msub_diff_sub0000_xor<2> + SLICE_X57Y127.F3 net (fanout=2) 0.448 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_sub0000<2> + SLICE_X57Y127.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_not0000<2>1_INV_0 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X57Y128.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<3> + SLICE_X57Y128.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Madd_diff_addsub0000_xor<5> + SLICE_X59Y128.F1 net (fanout=1) 1.010 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_addsub0000<5> + SLICE_X59Y128.CLK Tfck 0.235 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_mux0001<5>1 + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/diff_5 + ------------------------------------------------- --------------------------- + Total 9.585ns (3.424ns logic, 6.161ns route) + (35.7% logic, 64.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%; + + 1844 paths analyzed, 437 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 7.356ns. +-------------------------------------------------------------------------------- +Slack: 0.072ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 (FF) + Requirement: 3.750ns + Data Path Delay: 3.554ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: sdram_clk0 rising at 0.000ns + Destination Clock: sdram_clk0 falling at 3.750ns + Clock Uncertainty: 0.124ns + + Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X5Y170.G2 net (fanout=9) 1.258 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X5Y170.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_4_mux00041 + OLOGIC_X0Y182.D1 net (fanout=1) 1.115 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_4 + OLOGIC_X0Y182.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<4> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_4 + ------------------------------------------------- --------------------------- + Total 3.554ns (1.181ns logic, 2.373ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack: 0.134ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst (FF) + Requirement: 3.750ns + Data Path Delay: 3.492ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: sdram_clk0 rising at 0.000ns + Destination Clock: sdram_clk0 falling at 3.750ns + Clock Uncertainty: 0.124ns + + Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X19Y125.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg + SLICE_X1Y142.SR net (fanout=7) 2.065 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/we_reg + SLICE_X1Y142.CLK Tsrck 1.087 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_rst + ------------------------------------------------- --------------------------- + Total 3.492ns (1.427ns logic, 2.065ns route) + (40.9% logic, 59.1% route) + +-------------------------------------------------------------------------------- +Slack: 0.142ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 (FF) + Requirement: 3.750ns + Data Path Delay: 3.484ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: sdram_clk0 rising at 0.000ns + Destination Clock: sdram_clk0 falling at 3.750ns + Clock Uncertainty: 0.124ns + + Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y155.YQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X7Y175.G2 net (fanout=9) 1.403 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB3 + SLICE_X7Y175.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_6_mux00041 + OLOGIC_X0Y188.D1 net (fanout=1) 0.900 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_6 + OLOGIC_X0Y188.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<6> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_6 + ------------------------------------------------- --------------------------- + Total 3.484ns (1.181ns logic, 2.303ns route) + (33.9% logic, 66.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG; + + 24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) +-------------------------------------------------------------------------------- +Delay: 9.446ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) + Data Path Delay: 2.928ns (Levels of Logic = 1) + Clock Path Skew: -6.274ns (-2.389 - 3.885) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y164.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X7Y152.G3 net (fanout=20) 1.411 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X7Y152.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 + SLICE_X7Y153.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X7Y153.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + ------------------------------------------------- --------------------------- + Total 2.928ns (1.087ns logic, 1.841ns route) + (37.1% logic, 62.9% route) + +-------------------------------------------------------------------------------- +Delay: 9.421ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF) + Data Path Delay: 2.900ns (Levels of Logic = 1) + Clock Path Skew: -6.277ns (-2.389 - 3.888) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y161.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X7Y152.G1 net (fanout=9) 1.383 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 + SLICE_X7Y152.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141 + SLICE_X7Y153.CE net (fanout=1) 0.430 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke + SLICE_X7Y153.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 + ------------------------------------------------- --------------------------- + Total 2.900ns (1.087ns logic, 1.813ns route) + (37.5% logic, 62.5% route) + +-------------------------------------------------------------------------------- +Delay: 8.805ns (data path - clock path skew + uncertainty) + Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF) + Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF) + Data Path Delay: 2.320ns (Levels of Logic = 2) + Clock Path Skew: -6.241ns (-2.356 - 3.885) + Source Clock: CLK_O rising + Destination Clock: sdram_clk0 rising + Clock Uncertainty: 0.244ns + + Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.248ns + Phase Error (PE): 0.120ns + + Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y164.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X10Y154.F3 net (fanout=20) 1.411 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 + SLICE_X10Y154.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/data_reg_r<49> + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X10Y155.F4 net (fanout=1) 0.159 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9 + SLICE_X10Y155.CLK Tfck 0.215 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62 + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 + ------------------------------------------------- --------------------------- + Total 2.320ns (0.750ns logic, 1.570ns route) + (32.3% logic, 67.7% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%; + + 14750 paths analyzed, 701 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 7.990ns. +-------------------------------------------------------------------------------- +Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) + Requirement: 8.000ns + Data Path Delay: 7.674ns (Levels of Logic = 8) + Clock Path Skew: -0.181ns (2.507 - 2.688) + Source Clock: vga_clk rising at 0.000ns + Destination Clock: vga_clk rising at 8.000ns + Clock Uncertainty: 0.135ns + + Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.270ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y140.YQ Tcko 0.360 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt_1 + SLICE_X55Y140.G1 net (fanout=3) 0.593 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1> + SLICE_X55Y140.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<1>_rt + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X55Y141.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1> + SLICE_X55Y141.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X55Y142.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3> + SLICE_X55Y142.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/empty + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + SLICE_X55Y143.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5> + SLICE_X55Y143.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<6> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + SLICE_X55Y144.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7> + SLICE_X55Y144.YMUX Tciny 0.503 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<8> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<9> + SLICE_X53Y142.G2 net (fanout=1) 1.221 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<9> + SLICE_X53Y142.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<9>1 + SLICE_X53Y139.G2 net (fanout=10) 0.546 inst_vga_frontend/inst_linefifo/ptr_r<9> + SLICE_X53Y139.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<5> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<9>1 + SLICE_X53Y138.F1 net (fanout=1) 0.387 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<9> + SLICE_X53Y138.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/pre_empty + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> + RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + ------------------------------------------------- --------------------------- + Total 7.674ns (3.159ns logic, 4.515ns route) + (41.2% logic, 58.8% route) + +-------------------------------------------------------------------------------- +Slack: 0.017ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) + Requirement: 8.000ns + Data Path Delay: 7.631ns (Levels of Logic = 7) + Clock Path Skew: -0.217ns (2.507 - 2.724) + Source Clock: vga_clk rising at 0.000ns + Destination Clock: vga_clk rising at 8.000ns + Clock Uncertainty: 0.135ns + + Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.270ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X61Y168.XQ Tcko 0.340 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + SLICE_X56Y156.F3 net (fanout=8) 0.863 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v/state_FSM_FFd1 + SLICE_X56Y156.X Tilo 0.195 inst_vga_frontend/stat_scan + inst_vga_frontend/inst_vga_backend/is_scan1 + SLICE_X54Y144.G2 net (fanout=17) 0.826 inst_vga_frontend/stat_scan + SLICE_X54Y144.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<11> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc1 + SLICE_X53Y143.F4 net (fanout=12) 0.455 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc + SLICE_X53Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 + SLICE_X54Y140.F1 net (fanout=9) 0.607 inst_vga_frontend/inst_linefifo/ptr_r<0> + SLICE_X54Y140.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 + SLICE_X53Y136.F2 net (fanout=1) 0.730 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0> + SLICE_X53Y136.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + SLICE_X53Y137.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + SLICE_X53Y137.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X53Y138.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X53Y138.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> + RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + ------------------------------------------------- --------------------------- + Total 7.631ns (2.382ns logic, 5.249ns route) + (31.2% logic, 68.8% route) + +-------------------------------------------------------------------------------- +Slack: 0.020ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 (FF) + Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM) + Requirement: 8.000ns + Data Path Delay: 7.609ns (Levels of Logic = 7) + Clock Path Skew: -0.236ns (2.507 - 2.743) + Source Clock: vga_clk rising at 0.000ns + Destination Clock: vga_clk rising at 8.000ns + Clock Uncertainty: 0.135ns + + Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.270ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X62Y161.XQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 + inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 + SLICE_X56Y156.F4 net (fanout=9) 0.821 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd1 + SLICE_X56Y156.X Tilo 0.195 inst_vga_frontend/stat_scan + inst_vga_frontend/inst_vga_backend/is_scan1 + SLICE_X54Y144.G2 net (fanout=17) 0.826 inst_vga_frontend/stat_scan + SLICE_X54Y144.Y Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<11> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc1 + SLICE_X53Y143.F4 net (fanout=12) 0.455 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/rinc + SLICE_X53Y143.X Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 + SLICE_X54Y140.F1 net (fanout=9) 0.607 inst_vga_frontend/inst_linefifo/ptr_r<0> + SLICE_X54Y140.X Tilo 0.195 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/gcnt<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtg<0>1 + SLICE_X53Y136.F2 net (fanout=1) 0.730 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/gnxt_r<0> + SLICE_X53Y136.COUT Topcyf 0.573 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_lut<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<0> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + SLICE_X53Y137.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<1> + SLICE_X53Y137.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<2> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X53Y138.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<3> + SLICE_X53Y138.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/pre_empty + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<4> + inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mcompar_pre_empty_cmp_eq0000_cy<5> + RAMB16_X4Y15.ENB net (fanout=8) 1.768 inst_vga_frontend/inst_linefifo/pre_empty + RAMB16_X4Y15.CLKB Trcck_ENB 0.518 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 + ------------------------------------------------- --------------------------- + Total 7.609ns (2.402ns logic, 5.207ns route) + (31.6% logic, 68.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: PATH "TS_unrelate_VGA_path" TIG; + + 64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) +-------------------------------------------------------------------------------- +Delay: 6.486ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_2_6 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_6 (FF) + Data Path Delay: 5.945ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising + Destination Clock: vga_clk rising + Clock Uncertainty: 0.541ns + + Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.347ns + Phase Error (PE): 0.367ns + + Maximum Data Path: inst_vga_frontend/cg_color_2_6 to inst_vga_frontend/inst_vga_backend/vga_blue_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X42Y102.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_3 + inst_vga_frontend/cg_color_2_6 + SLICE_X65Y148.G2 net (fanout=2) 2.455 inst_vga_frontend/cg_color_2_6 + SLICE_X65Y148.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + OLOGIC_X2Y172.REV net (fanout=1) 1.639 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<6>0 + OLOGIC_X2Y172.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<6> + inst_vga_frontend/inst_vga_backend/vga_blue_6 + ------------------------------------------------- --------------------------- + Total 5.945ns (1.851ns logic, 4.094ns route) + (31.1% logic, 68.9% route) + +-------------------------------------------------------------------------------- +Delay: 6.242ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_2_3 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_3 (FF) + Data Path Delay: 5.701ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising + Destination Clock: vga_clk rising + Clock Uncertainty: 0.541ns + + Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.347ns + Phase Error (PE): 0.367ns + + Maximum Data Path: inst_vga_frontend/cg_color_2_3 to inst_vga_frontend/inst_vga_backend/vga_blue_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X42Y102.XQ Tcko 0.360 inst_vga_frontend/cg_color_2_3 + inst_vga_frontend/cg_color_2_3 + SLICE_X65Y146.G1 net (fanout=2) 2.369 inst_vga_frontend/cg_color_2_3 + SLICE_X65Y146.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 + OLOGIC_X2Y169.REV net (fanout=1) 1.481 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<3>0 + OLOGIC_X2Y169.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<3> + inst_vga_frontend/inst_vga_backend/vga_blue_3 + ------------------------------------------------- --------------------------- + Total 5.701ns (1.851ns logic, 3.850ns route) + (32.5% logic, 67.5% route) + +-------------------------------------------------------------------------------- +Delay: 6.202ns (data path - clock path skew + uncertainty) + Source: inst_vga_frontend/cg_color_2_4 (FF) + Destination: inst_vga_frontend/inst_vga_backend/vga_blue_4 (FF) + Data Path Delay: 5.661ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising + Destination Clock: vga_clk rising + Clock Uncertainty: 0.541ns + + Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.347ns + Phase Error (PE): 0.367ns + + Maximum Data Path: inst_vga_frontend/cg_color_2_4 to inst_vga_frontend/inst_vga_backend/vga_blue_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X44Y106.YQ Tcko 0.360 inst_vga_frontend/cg_color_2_4 + inst_vga_frontend/cg_color_2_4 + SLICE_X64Y146.G1 net (fanout=2) 2.349 inst_vga_frontend/cg_color_2_4 + SLICE_X64Y146.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 + inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 + OLOGIC_X2Y170.REV net (fanout=1) 1.460 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<4>0 + OLOGIC_X2Y170.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<4> + inst_vga_frontend/inst_vga_backend/vga_blue_4 + ------------------------------------------------- --------------------------- + Total 5.661ns (1.852ns logic, 3.809ns route) + (32.7% logic, 67.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%; + + 852048 paths analyzed, 11745 endpoints analyzed, 5 failing endpoints + 5 timing errors detected. (5 setup errors, 0 hold errors) + Minimum period is 10.018ns. +-------------------------------------------------------------------------------- +Slack: -0.118ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) + Destination: inst_mips_top/inst_pipeline/pc.nxt_25 (FF) + Requirement: 9.900ns + Data Path Delay: 9.875ns (Levels of Logic = 23) + Clock Path Skew: -0.083ns (2.876 - 2.959) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns + + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> + SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> + SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf + inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/EX_stage_exc23 + SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc + SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/sdu_ID_nop + SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/cop_pipe_ID_RFE31 + SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE + SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 + inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 + SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 + SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 + inst_mips_top/inst_pipeline/sdu_ID_stall + SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall + SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 + inst_mips_top/inst_pipeline/pc_nxt_not00011 + SLICE_X18Y38.CE net (fanout=32) 0.711 inst_mips_top/inst_pipeline/pc_nxt_not0001 + SLICE_X18Y38.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_25 + inst_mips_top/inst_pipeline/pc.nxt_25 + ------------------------------------------------- --------------------------- + Total 9.875ns (4.557ns logic, 5.318ns route) + (46.1% logic, 53.9% route) + +-------------------------------------------------------------------------------- +Slack: -0.115ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) + Destination: inst_mips_top/inst_pipeline/pc.nxt_7 (FF) + Requirement: 9.900ns + Data Path Delay: 9.867ns (Levels of Logic = 23) + Clock Path Skew: -0.088ns (2.871 - 2.959) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns + + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> + SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> + SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf + inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/EX_stage_exc23 + SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc + SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/sdu_ID_nop + SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/cop_pipe_ID_RFE31 + SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE + SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 + inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 + SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 + SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 + inst_mips_top/inst_pipeline/sdu_ID_stall + SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall + SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 + inst_mips_top/inst_pipeline/pc_nxt_not00011 + SLICE_X20Y37.CE net (fanout=32) 0.703 inst_mips_top/inst_pipeline/pc_nxt_not0001 + SLICE_X20Y37.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_7 + inst_mips_top/inst_pipeline/pc.nxt_7 + ------------------------------------------------- --------------------------- + Total 9.867ns (4.557ns logic, 5.310ns route) + (46.2% logic, 53.8% route) + +-------------------------------------------------------------------------------- +Slack: -0.098ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 (FF) + Destination: inst_mips_top/inst_pipeline/pc.nxt_6 (FF) + Requirement: 9.900ns + Data Path Delay: 9.855ns (Levels of Logic = 23) + Clock Path Skew: -0.083ns (1.216 - 1.299) + Source Clock: cpu_clk rising at 0.000ns + Destination Clock: cpu_clk rising at 9.900ns + Clock Uncertainty: 0.060ns + + Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.120ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_mips_top/inst_pipeline/EX_stage.reg_a_0 to inst_mips_top/inst_pipeline/pc.nxt_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y12.XQ Tcko 0.360 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.F2 net (fanout=8) 0.817 inst_mips_top/inst_pipeline/EX_stage.reg_a_0 + SLICE_X13Y10.COUT Topcyf 0.573 inst_mips_top/inst_biu/DAT_I_dmem_rd<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_lut<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<1> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<2> + SLICE_X13Y11.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<3> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<4> + SLICE_X13Y12.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/bcu_op_b<8> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<5> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<6> + SLICE_X13Y13.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_1 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<7> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<8> + SLICE_X13Y14.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_b_27 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<9> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<10> + SLICE_X13Y15.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<11> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<12> + SLICE_X13Y16.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<13> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<14> + SLICE_X13Y17.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.ctrl.alu.add_2 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<15> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<16> + SLICE_X13Y18.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/EX_stage.reg_a_12 + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<17> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<18> + SLICE_X13Y19.COUT Tbyp 0.086 inst_mips_top/inst_biu/DAT_I_dmem_rd<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<19> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<20> + SLICE_X13Y20.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<21> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<22> + SLICE_X13Y21.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<12> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<23> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<24> + SLICE_X13Y22.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<25> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<26> + SLICE_X13Y23.COUT Tbyp 0.086 inst_mips_top/inst_biu/inst_icache/tag_reg_inv<4> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<27> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<28> + SLICE_X13Y24.COUT Tbyp 0.086 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<29> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<30> + SLICE_X13Y25.YMUX Tciny 0.503 inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<32> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_cy<31> + inst_mips_top/inst_pipeline/inst_alu/Madd_sum_add0000_xor<32> + SLICE_X16Y36.F4 net (fanout=4) 1.115 inst_mips_top/inst_pipeline/inst_alu/sum_res<31> + SLICE_X16Y36.X Tilo 0.195 inst_mips_top/inst_pipeline/MEM_stage.events_in.alu_uvf + inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.G4 net (fanout=1) 0.535 inst_mips_top/inst_pipeline/EX_events_alu_alu_uvf + SLICE_X20Y34.Y Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/EX_stage_exc23 + SLICE_X20Y34.F4 net (fanout=17) 0.183 inst_mips_top/inst_pipeline/EX_stage_exc + SLICE_X20Y34.X Tilo 0.195 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + inst_mips_top/inst_pipeline/sdu_ID_nop + SLICE_X22Y34.G4 net (fanout=15) 0.375 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_nop + SLICE_X22Y34.Y Tilo 0.195 inst_mips_top/inst_cop/exc_state_FSM_FFd3 + inst_mips_top/inst_cop/cop_pipe_ID_RFE31 + SLICE_X24Y34.G4 net (fanout=6) 0.428 inst_mips_top/inst_cop/cop_pipe_ID_RFE + SLICE_X24Y34.Y Tilo 0.195 inst_mips_top/inst_pipeline/pc.pc_branch_1 + inst_mips_top/inst_pipeline/sdu_ID_stall_SW0 + SLICE_X27Y35.G4 net (fanout=2) 0.330 inst_mips_top/N178 + SLICE_X27Y35.Y Tilo 0.194 inst_mips_top/inst_cop/exc_state_FSM_FFd6 + inst_mips_top/inst_pipeline/sdu_ID_stall + SLICE_X19Y31.F4 net (fanout=4) 0.824 inst_mips_top/pipe_c0_ctrl_out_sdu_ID_stall + SLICE_X19Y31.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_nxt_not0001 + inst_mips_top/inst_pipeline/pc_nxt_not00011 + SLICE_X18Y19.CE net (fanout=32) 0.691 inst_mips_top/inst_pipeline/pc_nxt_not0001 + SLICE_X18Y19.CLK Tceck 0.554 inst_mips_top/inst_pipeline/pc.nxt_6 + inst_mips_top/inst_pipeline/pc.nxt_6 + ------------------------------------------------- --------------------------- + Total 9.855ns (4.557ns logic, 5.298ns route) + (46.2% logic, 53.8% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: PATH "TS_unrelate_CPU_path" TIG; + + 58068 paths analyzed, 854 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) +-------------------------------------------------------------------------------- +Delay: 8.192ns (data path) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F (RAM) + Data Path Delay: 8.192ns (Levels of Logic = 7) + Source Clock: CLK_O rising at 0.000ns + + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> + SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> + Mmux_ADDR_O251 + SLICE_X37Y67.G2 net (fanout=6) 0.930 ADDR_O<31> + SLICE_X37Y67.Y Tilo 0.194 SRDY_O_sdram + CYC_I_sdram_1 + SLICE_X37Y67.F4 net (fanout=1) 0.159 CYC_I_sdram_1/O + SLICE_X37Y67.X Tilo 0.194 SRDY_O_sdram + inst_sdram_ctrl_frontend_wb/rdy1 + SLICE_X39Y65.F3 net (fanout=6) 0.424 SRDY_O_sdram + SLICE_X39Y65.X Tilo 0.194 SRDY_I26 + SRDY_I26 + SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 + SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> + SRDY_I36 + SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I + SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> + SRDY_I_cpu + SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu + SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 + SLICE_X30Y34.F1 net (fanout=67) 1.936 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + ------------------------------------------------- --------------------------- + Total 8.192ns (1.719ns logic, 6.473ns route) + (21.0% logic, 79.0% route) + +-------------------------------------------------------------------------------- +Delay: 8.137ns (data path) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F (RAM) + Data Path Delay: 8.137ns (Levels of Logic = 7) + Source Clock: CLK_O rising at 0.000ns + + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> + SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> + Mmux_ADDR_O251 + SLICE_X37Y67.G2 net (fanout=6) 0.930 ADDR_O<31> + SLICE_X37Y67.Y Tilo 0.194 SRDY_O_sdram + CYC_I_sdram_1 + SLICE_X37Y67.F4 net (fanout=1) 0.159 CYC_I_sdram_1/O + SLICE_X37Y67.X Tilo 0.194 SRDY_O_sdram + inst_sdram_ctrl_frontend_wb/rdy1 + SLICE_X39Y65.F3 net (fanout=6) 0.424 SRDY_O_sdram + SLICE_X39Y65.X Tilo 0.194 SRDY_I26 + SRDY_I26 + SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 + SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> + SRDY_I36 + SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I + SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> + SRDY_I_cpu + SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu + SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 + SLICE_X32Y36.F1 net (fanout=67) 1.881 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + ------------------------------------------------- --------------------------- + Total 8.137ns (1.719ns logic, 6.418ns route) + (21.1% logic, 78.9% route) + +-------------------------------------------------------------------------------- +Delay: 8.117ns (data path) + Source: arb_gnt_0 (FF) + Destination: inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F (RAM) + Data Path Delay: 8.117ns (Levels of Logic = 7) + Source Clock: CLK_O rising at 0.000ns + + Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r/Mram_RAM64.SLICEM_F + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X36Y67.XQ Tcko 0.360 arb_gnt<0> + arb_gnt_0 + SLICE_X34Y65.G1 net (fanout=114) 1.226 arb_gnt<0> + SLICE_X34Y65.Y Tilo 0.195 inst_flash_port/ADDR_I_r<16> + Mmux_ADDR_O251 + SLICE_X34Y69.F4 net (fanout=6) 0.361 ADDR_O<31> + SLICE_X34Y69.X Tilo 0.195 N382 + CYC_I_flash_SW0 + SLICE_X39Y66.G4 net (fanout=2) 0.538 N382 + SLICE_X39Y66.Y Tilo 0.194 N102 + CYC_I_flash + SLICE_X39Y65.F2 net (fanout=39) 0.538 CYC_I_flash + SLICE_X39Y65.X Tilo 0.194 SRDY_I26 + SRDY_I26 + SLICE_X35Y51.G4 net (fanout=1) 0.581 SRDY_I26 + SLICE_X35Y51.Y Tilo 0.194 ADDR_O_cpu<31> + SRDY_I36 + SLICE_X35Y50.F1 net (fanout=7) 0.418 SRDY_I + SLICE_X35Y50.X Tilo 0.194 ADDR_O_cpu<16> + SRDY_I_cpu + SLICE_X33Y48.F1 net (fanout=1) 0.799 SRDY_I_cpu + SLICE_X33Y48.X Tilo 0.194 inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/bcnt<0> + inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<0>1 + SLICE_X30Y34.F1 net (fanout=67) 1.936 inst_mips_top/inst_biu/inst_bout_fifo/ptr_r<0> + ------------------------------------------------- --------------------------- + Total 8.117ns (1.720ns logic, 6.397ns route) + (21.2% logic, 78.8% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%; + + 787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum period is 5.205ns. +-------------------------------------------------------------------------------- +Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_1 (FF) + Requirement: 80.000ns + Data Path Delay: 5.096ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 80.000ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 + SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 + SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 + SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 + SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 + inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 + SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + inst_ac97_wb/inst_ac_io/cnt_not00021 + SLICE_X54Y12.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X54Y12.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_1 + ------------------------------------------------- --------------------------- + Total 5.096ns (1.690ns logic, 3.406ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_3 (FF) + Requirement: 80.000ns + Data Path Delay: 5.096ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 80.000ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 + SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 + SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 + SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 + SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 + inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 + SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + inst_ac97_wb/inst_ac_io/cnt_not00021 + SLICE_X54Y13.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X54Y13.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<2> + inst_ac97_wb/inst_ac_io/cnt_3 + ------------------------------------------------- --------------------------- + Total 5.096ns (1.690ns logic, 3.406ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- +Slack: 74.795ns (requirement - (data path - clock path skew + uncertainty)) + Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF) + Destination: inst_ac97_wb/inst_ac_io/cnt_2 (FF) + Requirement: 80.000ns + Data Path Delay: 5.096ns (Levels of Logic = 4) + Clock Path Skew: 0.000ns + Source Clock: CLK_O rising at 0.000ns + Destination Clock: CLK_O rising at 80.000ns + Clock Uncertainty: 0.109ns + + Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.000ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.217ns + Phase Error (PE): 0.000ns + + Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X54Y12.XQ Tcko 0.360 inst_ac97_wb/inst_ac_io/cnt<0> + inst_ac97_wb/inst_ac_io/cnt_0 + SLICE_X55Y15.G4 net (fanout=9) 1.142 inst_ac97_wb/inst_ac_io/cnt<0> + SLICE_X55Y15.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1 + SLICE_X55Y15.F4 net (fanout=1) 0.159 N963 + SLICE_X55Y15.X Tilo 0.194 inst_ac97_wb/inst_ac_io/N9 + inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2 + SLICE_X55Y17.G4 net (fanout=3) 0.358 inst_ac97_wb/inst_ac_io/N9 + SLICE_X55Y17.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_7_2 + inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001 + SLICE_X53Y25.G4 net (fanout=10) 0.828 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000 + SLICE_X53Y25.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002 + inst_ac97_wb/inst_ac_io/cnt_not00021 + SLICE_X54Y13.CE net (fanout=5) 0.919 inst_ac97_wb/inst_ac_io/cnt_not0002 + SLICE_X54Y13.CLK Tceck 0.554 inst_ac97_wb/inst_ac_io/cnt<2> + inst_ac97_wb/inst_ac_io/cnt_2 + ------------------------------------------------- --------------------------- + Total 5.096ns (1.690ns logic, 3.406ns route) + (33.2% logic, 66.8% route) + +-------------------------------------------------------------------------------- + + +1 constraint not met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock to Setup on destination clock sys_ac97_bit_clk +----------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +----------------+---------+---------+---------+---------+ +sys_ac97_bit_clk| 6.860| 3.451| | 2.366| +----------------+---------+---------+---------+---------+ + +Clock to Setup on destination clock sys_clk_in +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +sys_clk_in | 10.018| 4.756| 4.893| 3.181| +---------------+---------+---------+---------+---------+ + + +Timing summary: +--------------- + +Timing errors: 5 Score: 483 + +Constraints cover 1399013 paths, 0 nets, and 42608 connections + +Design statistics: + Minimum period: 10.018ns{1} (Maximum frequency: 99.820MHz) + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Sun Feb 07 20:07:12 2010 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 347 MB + + + diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp new file mode 100644 index 0000000..a1da64d --- /dev/null +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_map.mrp @@ -0,0 +1,1796 @@ +Release 10.1.03 Map K.39 (nt) +Xilinx Mapping Report File for Design 'mips_sys' + +Design Information +------------------ +Command Line : map -ise W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -p xc4vsx35-ff668-10 +-timing -logic_opt on -ol high -xe n -t 1 -register_duplication -global_opt on -retiming on -equivalent_register_removal +on -cm area -pr b -k 4 -power off -o mips_sys_map.ncd mips_sys.ngd mips_sys.pcf +Target Device : xc4vsx35 +Target Package : ff668 +Target Speed : -10 +Stepping Level : ES +Mapper Version : virtex4 -- $Revision: 1.1 $ +Mapped Date : Sun Feb 07 19:52:23 2010 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 69 +Logic Utilization: + Number of Slice Flip Flops: 5,368 out of 30,720 17% + Number of 4 input LUTs: 8,515 out of 30,720 27% +Logic Distribution: + Number of occupied Slices: 5,888 out of 15,360 38% + Number of Slices containing only related logic: 5,888 out of 5,888 100% + Number of Slices containing unrelated logic: 0 out of 5,888 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 8,913 out of 30,720 29% + Number used as logic: 7,515 + Number used as a route-thru: 398 + Number used as 16x1 RAMs: 6 + Number used for Dual Port RAMs: 792 + (Two LUTs used per Dual Port RAM) + Number used as Shift registers: 202 + Number of bonded IOBs: 226 out of 448 50% + IOB Flip Flops: 350 + IOB Dual-Data Rate Flops: 42 + Number of BUFG/BUFGCTRLs: 12 out of 32 37% + Number used as BUFGs: 12 + Number of FIFO16/RAMB16s: 51 out of 192 26% + Number used as RAMB16s: 51 + Number of DCM_ADVs: 4 out of 8 50% + Number of BSCAN_VIRTEX4s: 1 out of 4 25% + +Peak Memory Usage: 510 MB +Total REAL time to MAP completion: 8 mins 29 secs +Total CPU time to MAP completion: 8 mins 20 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Modular Design Summary +Section 11 - Timing Report +Section 12 - Configuration String Information +Section 13 - Control Set Information +Section 14 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:421 - DIB0 should be connected if WRITE_WIDTH_B is set to 18 (RAMB16 + symbol "inst_mips_top/inst_biu/inst_icache/inst_tag_ram/Mram_RAM1"). +WARNING:LIT:243 - Logical network sys_usb_d_15_IOBUF/N2 has no load. +WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 167 + more times for the following (max. 5 shown): + sys_usb_d_15_IOBUF/N3, + sys_usb_d_14_IOBUF/N2, + sys_usb_d_14_IOBUF/N3, + sys_usb_d_13_IOBUF/N2, + sys_usb_d_13_IOBUF/N3 + To see the details of these warning messages, please use the -detail switch. +WARNING:Pack:2549 - The register + "inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property + IOB=TRUE, but was not packed into the OLOGIC component. The output signal for + register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires + general routing. +WARNING:Pack:2549 - The register + "inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial" has the property + IOB=TRUE, but was not packed into the OLOGIC component. The output signal for + register symbol inst_uart_wb_1/inst_uart_tx/kcuart/pipeline_serial requires + general routing. +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_765". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_2" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_763". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_3" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_761". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_4" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_759". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_5" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_757". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_6" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_755". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_7" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_753". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_8" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_751". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_9" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_749". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_10" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_747". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_11" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_745". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_12" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_743". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_13" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_741". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_21" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_725". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_14" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_739". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_22" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_723". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_23" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_721". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_15" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_737". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_31" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_705". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_24" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_719". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_16" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_735". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_32" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_703". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_25" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_717". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_17" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_733". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_18" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_731". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_26" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_715". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_19" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_729". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_27" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_713". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_20" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_727". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_28" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_711". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_29" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_709". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive270_10_30" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/drive" does not + match the ILOGIC SR signal "N0_707". + +WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the + ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000". + +WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_data_tx_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "inst_ps2_wb_0/inst_ps2_core/data_tx2" does not match the + ILOGIC SR signal "inst_ps2_phy_0/Inst_debounce_data/output_and0000". + +WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the + ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000". + +WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_data_tx_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "inst_ps2_wb_1/inst_ps2_core/data_tx2" does not match the + ILOGIC SR signal "inst_ps2_phy_1/Inst_debounce_data/output_and0000". + +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4" has + the property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_4 + set/reset disagrees with another register in the OLOGIC component. +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3" has + the property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_3 + set/reset disagrees with another register in the OLOGIC component. +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2" has + the property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_2 + set/reset disagrees with another register in the OLOGIC component. +WARNING:Pack:2549 - The register + "inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. Register + inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/dqs_zen_0_1 + set/reset disagrees with another register in the OLOGIC component. +WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "N25" does not match the ILOGIC SR signal + "inst_ps2_phy_0/Inst_debounce_clk/output_and0000". + The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not + match the ILOGIC REV signal + "inst_ps2_phy_0/Inst_debounce_clk/output_and0001". + +WARNING:Pack:2549 - The register "inst_ps2_wb_0/inst_ps2_core/ps2_clk_tx_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "N25" does not match the ILOGIC SR signal + "inst_ps2_phy_0/Inst_debounce_clk/output_and0000". + The OLOGIC REV signal "inst_ps2_wb_0/inst_ps2_core/read_cs_FSM_FFd3" does not + match the ILOGIC REV signal + "inst_ps2_phy_0/Inst_debounce_clk/output_and0001". + +WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "N21" does not match the ILOGIC SR signal + "inst_ps2_phy_1/Inst_debounce_clk/output_and0000". + The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not + match the ILOGIC REV signal + "inst_ps2_phy_1/Inst_debounce_clk/output_and0001". + +WARNING:Pack:2549 - The register "inst_ps2_wb_1/inst_ps2_core/ps2_clk_tx_1" has + the property IOB=TRUE, but was not packed into the OLOGIC component. The + OLOGIC SR signal "N21" does not match the ILOGIC SR signal + "inst_ps2_phy_1/Inst_debounce_clk/output_and0000". + The OLOGIC REV signal "inst_ps2_wb_1/inst_ps2_core/read_cs_FSM_FFd3" does not + match the ILOGIC REV signal + "inst_ps2_phy_1/Inst_debounce_clk/output_and0001". + +WARNING:Pack:2548 - The register "inst_gpio_wb/gpi1_reg_7" has the property + IOB=TRUE, but was not packed into the ILOGIC component. The ILOGIC component + already contains an IFF1. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000026_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000028 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000011_f6/MUXF5.I0 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000231 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000016_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000024_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000032 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00007_f6/MUXF5.I0. + Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000030_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000351 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000035_f6/MUXF5.I0 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000034 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00005_f6/MUXF5.I0. + Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000271 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000012_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000251 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000025_f6/MUXF5.I0 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000331 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000033_f6/MUXF5.I0 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000036 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00003_f6/MUXF5.I0. + Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000312 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom00008_f6/MUXF5.I1. + Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Pack:266 - The function generator + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom0000291 failed to + merge with F5 multiplexer + inst_mips_top/inst_pipeline/inst_shifter/Mrom_fill_mask_rom000010_f6/MUXF5.I1 + . Tried to combine two collections of symbols from different layers. The + alignment requirements of the two layers conflict. The design will exhibit + suboptimal timing. +WARNING:Place:838 - An IO Bus with more than one IO standard is found. + Components associated with this bus are as follows: + Comp: sys_vga_blue<0> IOSTANDARD = LVCMOS33 + Comp: sys_vga_blue<1> IOSTANDARD = LVCMOS33 + Comp: sys_vga_blue<2> IOSTANDARD = LVCMOS33 + Comp: sys_vga_blue<3> IOSTANDARD = LVCMOS25 + Comp: sys_vga_blue<4> IOSTANDARD = LVCMOS25 + Comp: sys_vga_blue<5> IOSTANDARD = LVCMOS25 + Comp: sys_vga_blue<6> IOSTANDARD = LVCMOS25 + Comp: sys_vga_blue<7> IOSTANDARD = LVCMOS25 + + +WARNING:Place:838 - An IO Bus with more than one IO standard is found. + Components associated with this bus are as follows: + Comp: sys_vga_green<0> IOSTANDARD = LVCMOS33 + Comp: sys_vga_green<1> IOSTANDARD = LVCMOS33 + Comp: sys_vga_green<2> IOSTANDARD = LVCMOS33 + Comp: sys_vga_green<3> IOSTANDARD = LVCMOS25 + Comp: sys_vga_green<4> IOSTANDARD = LVCMOS25 + Comp: sys_vga_green<5> IOSTANDARD = LVCMOS25 + Comp: sys_vga_green<6> IOSTANDARD = LVCMOS25 + Comp: sys_vga_green<7> IOSTANDARD = LVCMOS25 + + +WARNING:Place:838 - An IO Bus with more than one IO standard is found. + Components associated with this bus are as follows: + Comp: sys_vga_red<0> IOSTANDARD = LVCMOS33 + Comp: sys_vga_red<1> IOSTANDARD = LVCMOS33 + Comp: sys_vga_red<2> IOSTANDARD = LVCMOS33 + Comp: sys_vga_red<3> IOSTANDARD = LVCMOS25 + Comp: sys_vga_red<4> IOSTANDARD = LVCMOS25 + Comp: sys_vga_red<5> IOSTANDARD = LVCMOS25 + Comp: sys_vga_red<6> IOSTANDARD = LVCMOS25 + Comp: sys_vga_red<7> IOSTANDARD = LVCMOS25 + + +WARNING:Place:957 - Placer has detected that XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING + has been set. This environment variable has been deprecated. An ERROR in + clock placement rules can be demoted to a WARNING by using the + CLOCK_DEDICATED_ROUTE constraint on a specific component pin in the .ucf + file. +WARNING:PhysDesignRules:1236 - Unknown DCM_ADV feedback loop. The signal sys_sdr_clk_fb_IBUFG on the CLKFB pin of + DCM_ADV comp inst_clockgen/inst_DCM_SDRCLK_0 was driven by an IOB site but the signal loop could not be traced back + to the CLK0 pin of comp inst_clockgen/inst_DCM_SDRCLK_0. The signal out the CLK0 pin must drive an IOB input pin with + programming out to the PAD. + +Section 3 - Informational +------------------------- +INFO:MapLib:564 - The following environment variables are currently set: +INFO:MapLib:591 - XIL_MAP_LOCWARN Value: 1 +INFO:MapLib:159 - Net Timing constraints on signal sys_ac97_bit_clk are pushed + forward through input buffer. +INFO:MapLib:797 - Your design is targeting LX/SX Production Step 0/1/ES devices. + Please note that there are new specifications for the DCMs to guarantee + maximum frequency performance. If the DCM input clock might stop or if the + DCM reset might be asserted for an extended time, then use of the dcm_standby + macro may be required. Please see Answer Record 21127. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to + 1.260 Volts) +INFO:Pack:1650 - Map created a placed design. +INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of + the DCM_ADV comp inst_clockgen/inst_DCM_VGA_FX, consult the device Data Sheet. +INFO:PhysDesignRules:1437 - To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of + the DCM_ADV comp inst_clockgen/inst_DCM_SYS_FX, consult the device Data Sheet. + +Section 4 - Removed Logic Summary +--------------------------------- + 168 block(s) removed + 4 block(s) optimized away + 168 signal(s) removed + +Section 5 - Removed Logic +------------------------- + +The trimmed logic report below shows the logic removed from your design due to +sourceless or loadless signals, and VCC or ground connections. If the removal +of a signal or symbol results in the subsequent removal of an additional signal +or symbol, the message explaining that second removal will be indented. This +indentation will be repeated as a chain of related logic is removed. + +To quickly locate the original cause for the removal of a chain of logic, look +above the place where that logic is listed in the trimming report, then locate +the lines that are least indented (begin at the leftmost edge). + +The signal "sys_usb_d_15_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_15_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_14_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_14_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_13_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_13_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_12_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_12_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_11_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_11_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_10_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_10_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_9_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_9_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_8_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_8_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_7_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_7_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_6_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_6_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_5_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_5_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_4_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_4_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_3_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_3_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_2_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_2_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_1_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_1_IOBUF/N3" is sourceless and has been removed. +The signal "sys_usb_d_0_IOBUF/N2" is sourceless and has been removed. +The signal "sys_usb_d_0_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_31_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_31_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_30_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_30_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_29_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_29_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_28_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_28_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_27_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_27_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_26_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_26_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_25_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_25_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_24_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_24_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_23_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_23_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_22_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_22_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_21_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_21_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_20_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_20_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_19_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_19_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_18_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_18_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_17_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_17_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_16_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_16_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_15_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_15_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_14_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_14_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_13_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_13_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_12_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_12_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_11_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_11_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_10_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_10_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_9_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_9_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_8_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_8_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_7_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_7_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_6_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_6_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_5_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_5_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_4_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_4_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_3_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_3_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_2_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_2_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_1_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_1_IOBUF/N3" is sourceless and has been removed. +The signal "sys_flash_d_0_IOBUF/N2" is sourceless and has been removed. +The signal "sys_flash_d_0_IOBUF/N3" is sourceless and has been removed. +The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N2" is sourceless and has been +removed. +The signal "inst_ps2_phy_1/IOBUF_inst_ps2_data/N3" is sourceless and has been +removed. +The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N2" is sourceless and has been +removed. +The signal "inst_ps2_phy_1/IOBUF_inst_ps2_clk/N3" is sourceless and has been +removed. +The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N2" is sourceless and has been +removed. +The signal "inst_ps2_phy_0/IOBUF_inst_ps2_data/N3" is sourceless and has been +removed. +The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N2" is sourceless and has been +removed. +The signal "inst_ps2_phy_0/IOBUF_inst_ps2_clk/N3" is sourceless and has been +removed. +The signal "sys_sdr_data_31_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_31_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_30_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_30_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_29_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_29_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_28_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_28_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_27_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_27_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_26_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_26_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_25_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_25_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_24_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_24_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_23_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_23_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_22_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_22_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_21_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_21_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_20_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_20_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_19_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_19_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_18_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_18_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_17_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_17_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_16_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_16_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_15_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_15_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_14_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_14_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_13_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_13_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_12_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_12_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_11_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_11_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_10_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_10_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_9_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_9_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_8_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_8_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_7_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_7_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_6_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_6_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_5_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_5_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_4_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_4_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_3_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_3_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_2_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_2_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_1_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_1_IOBUF/N3" is sourceless and has been removed. +The signal "sys_sdr_data_0_IOBUF/N2" is sourceless and has been removed. +The signal "sys_sdr_data_0_IOBUF/N3" is sourceless and has been removed. +Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed. +Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed. +Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed. +Unused block "inst_ps2_phy_0/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed. +Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_GND" (ZERO) removed. +Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_clk/XST_VCC" (ONE) removed. +Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_GND" (ZERO) removed. +Unused block "inst_ps2_phy_1/IOBUF_inst_ps2_data/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_0_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_0_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_10_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_10_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_11_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_11_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_12_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_12_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_13_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_13_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_14_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_14_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_15_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_15_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_16_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_16_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_17_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_17_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_18_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_18_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_19_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_19_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_1_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_1_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_20_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_20_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_21_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_21_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_22_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_22_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_23_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_23_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_24_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_24_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_25_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_25_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_26_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_26_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_27_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_27_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_28_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_28_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_29_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_29_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_2_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_2_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_30_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_30_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_31_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_31_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_3_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_3_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_4_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_4_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_5_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_5_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_6_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_6_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_7_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_7_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_8_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_8_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_flash_d_9_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_flash_d_9_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_0_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_0_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_10_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_10_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_11_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_11_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_12_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_12_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_13_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_13_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_14_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_14_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_15_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_15_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_16_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_16_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_17_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_17_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_18_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_18_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_19_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_19_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_1_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_1_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_20_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_20_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_21_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_21_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_22_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_22_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_23_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_23_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_24_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_24_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_25_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_25_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_26_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_26_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_27_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_27_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_28_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_28_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_29_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_29_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_2_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_2_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_30_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_30_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_31_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_31_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_3_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_3_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_4_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_4_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_5_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_5_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_6_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_6_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_7_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_7_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_8_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_8_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_sdr_data_9_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_sdr_data_9_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_0_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_0_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_10_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_10_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_11_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_11_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_12_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_12_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_13_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_13_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_14_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_14_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_15_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_15_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_1_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_1_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_2_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_2_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_3_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_3_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_4_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_4_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_5_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_5_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_6_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_6_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_7_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_7_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_8_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_8_IOBUF/XST_VCC" (ONE) removed. +Unused block "sys_usb_d_9_IOBUF/XST_GND" (ZERO) removed. +Unused block "sys_usb_d_9_IOBUF/XST_VCC" (ONE) removed. + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC +GND inst_mips_top/XST_GND +VCC inst_mips_top/XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Strength | Rate | | | Delay | ++-------------------------------------------------------------------------------------------------------------------------------------------------+ +| sys_ac97_bit_clk | IOB | INPUT | LVCMOS33 | | | | | | +| sys_ac97_sdata_in | IOB | INPUT | LVCMOS33 | | | IFF1 | | | +| sys_ac97_sdata_out | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | | +| sys_ac97_ssync | IOB | OUTPUT | LVCMOS25 | 12 | FAST | OFF1 | | | +| sys_btn<0> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | +| sys_btn<1> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | +| sys_btn<2> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | +| sys_btn<3> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | +| sys_btn<4> | IOB | INPUT | LVCMOS25 | | | IFF1 | PULLDOWN | | +| sys_clk_in | IOB | INPUT | LVCMOS33 | | | | | | +| sys_dip<0> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<1> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<2> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<3> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<4> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<5> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<6> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_dip<7> | IOB | INPUT | LVCMOS33 | | | IFF1 | PULLDOWN | | +| sys_error<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | | +| sys_error<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | OFF1 | | | +| sys_flash_a<0> | IOB | OUTPUT | LVDCI_33 | | | | | | +| sys_flash_a<1> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<2> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<3> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<4> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<5> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<6> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<7> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<8> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<9> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<10> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<11> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<12> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<13> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<14> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<15> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<16> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<17> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<18> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<19> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<20> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<21> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<22> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<23> | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_a<24> | IOB | OUTPUT | LVDCI_33 | | | | | | +| sys_flash_ac97_rstn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | +| sys_flash_byten | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | +| sys_flash_ce | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_d<0> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<1> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<2> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<3> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<4> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<5> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<6> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<7> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<8> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<9> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<10> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<11> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<12> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<13> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<14> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<15> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<16> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<17> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<18> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<19> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<20> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<21> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<22> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<23> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<24> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<25> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<26> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<27> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<28> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<29> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<30> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_d<31> | IOB | BIDIR | LVCMOS33 | 12 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_flash_rdn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_flash_wrn | IOB | OUTPUT | LVDCI_33 | | | OFF1 | | | +| sys_lcd_d<0> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | +| sys_lcd_d<1> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | +| sys_lcd_d<2> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | +| sys_lcd_d<3> | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | PULLDOWN | | +| sys_lcd_e | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | +| sys_lcd_rs | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | +| sys_lcd_rw | IOB | OUTPUT | LVCMOS33 | 2 | SLOW | | | | +| sys_led<0> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<1> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<2> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<3> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<4> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<5> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<6> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<7> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_led<8> | IOB | OUTPUT | LVCMOS25 | 2 | SLOW | OFF1 | | | +| sys_ps2_0_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | +| sys_ps2_0_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | +| sys_ps2_1_clk | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | +| sys_ps2_1_data | IOB | BIDIR | LVCMOS25 | 2 | SLOW | IFF1 | | | +| sys_rst_n_in | IOB | INPUT | LVCMOS25 | | | | PULLUP | | +| sys_sdr_a_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<2> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<3> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<4> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<5> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<6> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<7> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<8> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<9> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<10> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<11> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_a_q<12> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_ba_q<0> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_ba_q<1> | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_cas_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_cke_q | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_clk_fb | IOB | INPUT | LVCMOS25 | | | | | | +| sys_sdr_clk_n | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_clk_p | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_cs_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_data<0> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<1> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<2> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<3> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<4> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<5> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<6> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<7> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<8> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<9> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<10> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<11> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<12> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<13> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<14> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<15> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<16> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<17> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<18> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<19> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<20> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<21> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<22> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<23> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<24> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<25> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<26> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<27> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<28> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<29> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<30> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_data<31> | IOB | BIDIR | SSTL2_II | | | IFF1 | | | +| | IDDR:SAMEODDR:SA | | | | | IFF2 | | | +| | | | | | | IFF4 | | | +| | | | | | | OFF1 | | | +| | | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_dm_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:SAME | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_dm_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:SAME | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_dm_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:SAME | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_dm_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:SAME | | | | | OFF2 | | | +| | | | | | | OFF3 | | | +| | | | | | | OFFDDRB | | | +| sys_sdr_dqs_q<0> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_dqs_q<1> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_dqs_q<2> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_dqs_q<3> | IOB | OUTPUT | SSTL2_II | | | OFF1 | | | +| | ODDR:OPPOSITE | | | | | OFF2 | | | +| | | | | | | OFFDDRA | | | +| sys_sdr_ras_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_sdr_we_qn | IOB | OUTPUT | SSTL2_I | | | OFF1 | | | +| sys_uart0_rx | IOB | INPUT | LVCMOS33 | | | IFF1 | | | +| sys_uart0_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | +| sys_uart1_rx | IOB | INPUT | LVCMOS33 | | | | | | +| sys_uart1_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | +| sys_uart2_rx | IOB | INPUT | LVCMOS33 | | | | | | +| sys_uart2_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | +| sys_uart3_rx | IOB | INPUT | LVCMOS33 | | | | | | +| sys_uart3_tx | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | | | | +| sys_usb_a<0> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | +| sys_usb_a<1> | IOB | OUTPUT | LVCMOS33 | 12 | SLOW | OFF1 | | | +| sys_usb_csn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_usb_d<0> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<1> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<2> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<3> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<4> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<5> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<6> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<7> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<8> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<9> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<10> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<11> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<12> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<13> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<14> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_d<15> | IOB | BIDIR | LVCMOS33 | 8 | FAST | IFF1 | PULLDOWN | | +| | | | | | | OFF1 | | | +| | | | | | | TFF1 | | | +| sys_usb_int | IOB | INPUT | LVCMOS33 | | | | PULLDOWN | | +| sys_usb_rdn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_usb_rstn | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | | +| sys_usb_wrn | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_blank_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | +| sys_vga_blue<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_blue<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_blue<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_blue<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_blue<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_blue<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_blue<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_blue<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_clk | IOB | OUTPUT | LVDCI_33 | | | | | | +| sys_vga_green<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_green<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_green<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_green<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_green<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_green<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_green<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_green<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_hsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_red<0> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_red<1> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_red<2> | IOB | OUTPUT | LVCMOS33 | 8 | FAST | OFF1 | | | +| sys_vga_red<3> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_red<4> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_red<5> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_red<6> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_red<7> | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | +| sys_vga_sync_n | IOB | OUTPUT | LVCMOS33 | 8 | FAST | | | | +| sys_vga_vsync | IOB | OUTPUT | LVCMOS25 | 8 | FAST | OFF1 | | | ++-------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + +Area Group "AG_inst_mips_top" + No COMPRESSION specified for Area Group "AG_inst_mips_top" + RANGE: SLICE_X0Y53:SLICE_X39Y0 + RANGE: +RAMB16_X0Y0:RAMB16_X0Y6,RAMB16_X1Y0:RAMB16_X1Y6,RAMB16_X2Y0:RAMB16_X2Y6,RAMB16_X +3Y0:RAMB16_X3Y6 + Area Group Logic Utilization: + Number of Slice Flip Flops: 1,915 out of 4,320 44% + Logic Distribution: + Number of occupied Slices: 2,148 out of 2,160 99% + Number of Slices containing only related logic: 2,148 out of 2,148 100% + Total Number of 4 input LUTs: 4,220 out of 4,320 97% + Number used as logic: 3,551 + Number used as route-thru: 58 + Number used as 16x1 RAMs: 2 + Number used as Dual Port RAMs: 586 + (Two LUTs used per Dual Port RAM) + Number used as Shift registers: 23 + Number of Block RAMs: 27 out of 28 96% + + +Section 10 - Modular Design Summary +----------------------------------- +Modular Design not used for this design. + +Section 11 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Development System Reference Guide "TRACE" chapter. + +Section 12 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 13 - Control Set Information +------------------------------------ +No control set information for this architecture. + +Section 14 - Utilization by Hierarchy +------------------------------------- ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48 | BUFG | BUFIO | BUFR | DCM | Full Hierarchical Name | ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +| mips_sys/ | | 1399/8096 | 28/5368 | 848/8913 | 2/1000 | 0/51 | 0/0 | 2/12 | 0/0 | 0/0 | 0/4 | mips_sys | +| +inst_ac97_wb | | 183/793 | 118/671 | 186/616 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb | +| ++inst_ac_io | | 22/579 | 13/524 | 29/377 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io | +| +++inst_ac_in | | 269/275 | 258/262 | 98/103 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in | +| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst1 | +| ++++singleshot_inst2 | | 3/3 | 2/2 | 3/3 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_in/singleshot_inst2 | +| +++inst_ac_out | | 279/282 | 247/249 | 243/245 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out | +| ++++singleshot_inst1 | | 3/3 | 2/2 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_ac_io/inst_ac_out/singleshot_inst1 | +| ++inst_tx_fifo | | 1/31 | 0/29 | 1/53 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo | +| +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 29/29 | 29/29 | 51/51 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ac97_wb/inst_tx_fifo/inst_fifo_sync_ctrl | +| +inst_clockgen | | 51/57 | 54/54 | 18/24 | 4/10 | 0/0 | 0/0 | 8/8 | 0/0 | 0/0 | 4/4 | mips_sys/inst_clockgen | +| ++Mshreg_reset_pipe0_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_0 | +| ++Mshreg_reset_pipe0_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe0_19_1 | +| ++Mshreg_reset_pipe1_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_0 | +| ++Mshreg_reset_pipe1_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe1_19_1 | +| ++Mshreg_reset_pipe2_19_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_0 | +| ++Mshreg_reset_pipe2_19_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_clockgen/Mshreg_reset_pipe2_19_1 | +| +inst_flash_port | | 79/79 | 64/64 | 49/49 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_flash_port | +| +inst_gpio_wb | | 267/267 | 298/298 | 433/433 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_gpio_wb | +| +inst_mips_top | | 20/2827 | 22/1916 | 13/4118 | 2/611 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top | +| ++Mshreg_reset_delay_15 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_15 | +| ++Mshreg_reset_delay_19 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_19 | +| ++Mshreg_reset_delay_30 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/Mshreg_reset_delay_30 | +| ++inst_biu | | 188/802 | 97/536 | 208/911 | 0/350 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu | +| +++inst_bin_fifo | | 4/102 | 0/62 | 4/107 | 0/74 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo | +| ++++inst_dpram_1w1r | | 57/57 | 32/32 | 64/64 | 64/64 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 13/41 | 12/30 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl | +| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | +| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| +++++inst_gray_counter_r | | 8/8 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_w | | 10/10 | 9/9 | 12/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bin_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_bout_fifo | | 3/146 | 0/99 | 3/176 | 0/144 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo | +| ++++inst_dpram_1w1r | | 101/101 | 67/67 | 134/134 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 13/42 | 14/32 | 5/39 | 0/10 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl | +| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| +++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | +| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| +++++inst_gray_counter_r | | 8/8 | 9/9 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_w | | 11/11 | 9/9 | 13/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_bout_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_dcache | | 167/167 | 120/120 | 148/148 | 0/0 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache | +| ++++gen_data_ram[0].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[0].inst_data_ram | +| ++++gen_data_ram[1].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[1].inst_data_ram | +| ++++gen_data_ram[2].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[2].inst_data_ram | +| ++++gen_data_ram[3].inst_data_ra | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/gen_data_ram[3].inst_data_ram | +| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_dcache/inst_tag_ram | +| +++inst_icache | | 118/118 | 81/81 | 120/120 | 0/0 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache | +| ++++inst_data_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_data_ram | +| ++++inst_tag_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_icache/inst_tag_ram | +| +++inst_write_fifo | | 1/81 | 0/77 | 1/152 | 0/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo | +| ++++inst_dpram_1w1r | | 67/67 | 66/66 | 133/133 | 132/132 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_dpram_1w1r | +| ++++inst_fifo_sync_ctrl | | 13/13 | 11/11 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_biu/inst_write_fifo/inst_fifo_sync_ctrl | +| ++inst_cop | | 214/214 | 190/190 | 239/239 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_cop | +| ++inst_pipeline | | 875/1788 | 641/1168 | 1296/2952 | 0/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline | +| +++inst_alu | | 63/63 | 1/1 | 119/119 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_alu | +| +++inst_bcu | | 8/8 | 0/0 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_bcu | +| +++inst_muldiv | | 555/555 | 526/526 | 1025/1025 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_muldiv | +| +++inst_reg_dual | | 128/128 | 0/0 | 256/256 | 256/256 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_reg_dual | +| +++inst_shifter | | 159/159 | 0/0 | 240/240 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_mips_top/inst_pipeline/inst_shifter | +| +inst_ps2_phy_0 | | 0/13 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0 | +| ++Inst_debounce_clk | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_clk | +| ++Inst_debounce_data | | 7/7 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_0/Inst_debounce_data | +| +inst_ps2_phy_1 | | 0/11 | 0/10 | 0/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1 | +| ++Inst_debounce_clk | | 5/5 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_clk | +| ++Inst_debounce_data | | 6/6 | 5/5 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_phy_1/Inst_debounce_data | +| +inst_ps2_wb_0 | | 33/157 | 30/139 | 23/169 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0 | +| ++inst_ps2_core | | 124/124 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_0/inst_ps2_core | +| +inst_ps2_wb_1 | | 30/146 | 30/139 | 21/167 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1 | +| ++inst_ps2_core | | 116/116 | 109/109 | 146/146 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_ps2_wb_1/inst_ps2_core | +| +inst_rom_wb | | 1/72 | 1/99 | 1/53 | 0/2 | 0/4 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb | +| ++inst_rom | | 71/71 | 98/98 | 52/52 | 2/2 | 4/4 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | mips_sys/inst_rom_wb/inst_rom | +| +inst_sdram_ctrl_frontend_wb | | 97/649 | 0/455 | 145/599 | 0/39 | 0/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb | +| ++inst_cat_fifo | | 1/16 | 0/13 | 1/24 | 0/0 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo | +| +++inst_dpram_1w1r | | 1/1 | 0/0 | 1/1 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 14/14 | 13/13 | 22/22 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_cat_fifo/inst_fifo_sync_ctrl | +| ++inst_read_fifo | | 5/56 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_dpram_1w1r | +| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl | +| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | +| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | +| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | +| ++++inst_gray_counter_r | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_read_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_sdram_ctrl | | 0/424 | 0/370 | 0/320 | 0/15 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl | +| +++inst_ddr_phy | | 171/172 | 216/216 | 2/3 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy | +| ++++Mshreg_u_tag_pipe_4_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/Mshreg_u_tag_pipe_4_0 | +| +++inst_sd_cmd_fifo | | 3/65 | 0/41 | 4/60 | 0/14 | 0/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo | +| ++++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r | +| ++++inst_fifo_async_ctrl | | 23/62 | 17/41 | 11/56 | 0/14 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl | +| +++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| +++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| +++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| +++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| +++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | +| +++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| +++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| +++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| +++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| +++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| +++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | +| +++++Mshreg_p2_2_BRB0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB0 | +| +++++Mshreg_p2_2_BRB1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB1 | +| +++++Mshreg_p2_2_BRB2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/Mshreg_p2_2_BRB2 | +| +++++inst_gray_counter_r | | 15/15 | 13/13 | 16/16 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| +++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +++inst_sdram_cmd | | 47/47 | 13/13 | 66/66 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd | +| +++inst_sdram_ctrl | | 140/140 | 100/100 | 191/191 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl | +| ++inst_write_fifo | | 5/56 | 0/36 | 6/55 | 0/12 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_dpram_1w1r | +| +++inst_fifo_async_ctrl | | 18/51 | 14/36 | 7/49 | 0/12 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl | +| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | +| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | +| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | +| ++++inst_gray_counter_r | | 11/11 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 10/10 | 11/11 | 15/15 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_sdram_ctrl_frontend_wb/inst_write_fifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| +inst_uart_wb_0 | | 58/103 | 64/106 | 43/111 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0 | +| ++inst_uart_rx | | 0/28 | 0/28 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx | +| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/buf | +| +++kcuart | | 20/20 | 23/23 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/17 | 0/14 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx | +| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/buf | +| +++kcuart | | 9/9 | 9/9 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_0/inst_uart_tx/kcuart | +| +inst_uart_wb_1 | | 56/105 | 64/108 | 42/110 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1 | +| ++inst_uart_rx | | 0/30 | 0/29 | 0/38 | 0/27 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx | +| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/buf | +| +++kcuart | | 22/22 | 24/24 | 22/22 | 19/19 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_rx/kcuart | +| ++inst_uart_tx | | 0/19 | 0/15 | 0/30 | 0/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx | +| +++buf | | 8/8 | 5/5 | 16/16 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/buf | +| +++kcuart | | 11/11 | 10/10 | 14/14 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_uart_wb_1/inst_uart_tx/kcuart | +| +inst_usb_port | | 30/30 | 26/26 | 26/26 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_usb_port | +| +inst_vga_frontend | | 783/1388 | 793/1245 | 766/1554 | 0/264 | 0/13 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend | +| ++inst_blitfifo | | 1/25 | 0/21 | 1/40 | 0/0 | 0/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 24/24 | 21/21 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_blitfifo/inst_fifo_sync_ctrl | +| ++inst_bus_fifo | | 1/114 | 0/110 | 1/219 | 0/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo | +| +++inst_dpram_1w1r | | 104/104 | 103/103 | 207/207 | 206/206 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_dpram_1w1r | +| +++inst_fifo_sync_ctrl | | 9/9 | 7/7 | 11/11 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_bus_fifo/inst_fifo_sync_ctrl | +| ++inst_char_gen | | 180/192 | 126/126 | 240/252 | 0/12 | 0/4 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen | +| +++Mshreg_csr_posx_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_0 | +| +++Mshreg_csr_posx_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_1 | +| +++Mshreg_csr_posx_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_2 | +| +++Mshreg_csr_posx_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_3 | +| +++Mshreg_csr_posx_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_4 | +| +++Mshreg_csr_posx_synced_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_5 | +| +++Mshreg_csr_posx_synced_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posx_synced_6 | +| +++Mshreg_csr_posy_synced_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_0 | +| +++Mshreg_csr_posy_synced_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_1 | +| +++Mshreg_csr_posy_synced_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_2 | +| +++Mshreg_csr_posy_synced_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_3 | +| +++Mshreg_csr_posy_synced_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/Mshreg_csr_posy_synced_4 | +| +++inst_ascii_ram | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_ascii_ram | +| +++inst_char_rom | | 0/0 | 0/0 | 0/0 | 0/0 | 2/2 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_char_gen/inst_char_rom | +| ++inst_linefifo | | 1/172 | 0/145 | 1/179 | 0/46 | 0/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo | +| +++inst_dpram_1w1r | | 0/0 | 0/0 | 0/0 | 0/0 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_dpram_1w1r | +| +++inst_fifo_async_ctrl | | 85/171 | 87/145 | 84/178 | 0/46 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl | +| ++++Mshreg_bcnt2_ar_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_0 | +| ++++Mshreg_bcnt2_ar_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_1 | +| ++++Mshreg_bcnt2_ar_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_10 | +| ++++Mshreg_bcnt2_ar_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_11 | +| ++++Mshreg_bcnt2_ar_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_2 | +| ++++Mshreg_bcnt2_ar_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_3 | +| ++++Mshreg_bcnt2_ar_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_4 | +| ++++Mshreg_bcnt2_ar_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_5 | +| ++++Mshreg_bcnt2_ar_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_6 | +| ++++Mshreg_bcnt2_ar_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_7 | +| ++++Mshreg_bcnt2_ar_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_8 | +| ++++Mshreg_bcnt2_ar_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_ar_9 | +| ++++Mshreg_bcnt2_aw_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_0 | +| ++++Mshreg_bcnt2_aw_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_1 | +| ++++Mshreg_bcnt2_aw_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_10 | +| ++++Mshreg_bcnt2_aw_11 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_11 | +| ++++Mshreg_bcnt2_aw_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_2 | +| ++++Mshreg_bcnt2_aw_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_3 | +| ++++Mshreg_bcnt2_aw_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_4 | +| ++++Mshreg_bcnt2_aw_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_5 | +| ++++Mshreg_bcnt2_aw_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_6 | +| ++++Mshreg_bcnt2_aw_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_7 | +| ++++Mshreg_bcnt2_aw_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_8 | +| ++++Mshreg_bcnt2_aw_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_bcnt2_aw_9 | +| ++++Mshreg_gcnt2_r_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_0 | +| ++++Mshreg_gcnt2_r_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_1 | +| ++++Mshreg_gcnt2_r_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_10 | +| ++++Mshreg_gcnt2_r_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_2 | +| ++++Mshreg_gcnt2_r_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_3 | +| ++++Mshreg_gcnt2_r_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_4 | +| ++++Mshreg_gcnt2_r_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_5 | +| ++++Mshreg_gcnt2_r_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_6 | +| ++++Mshreg_gcnt2_r_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_7 | +| ++++Mshreg_gcnt2_r_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_8 | +| ++++Mshreg_gcnt2_r_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_r_9 | +| ++++Mshreg_gcnt2_w_0 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_0 | +| ++++Mshreg_gcnt2_w_1 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_1 | +| ++++Mshreg_gcnt2_w_10 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_10 | +| ++++Mshreg_gcnt2_w_2 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_2 | +| ++++Mshreg_gcnt2_w_3 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_3 | +| ++++Mshreg_gcnt2_w_4 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_4 | +| ++++Mshreg_gcnt2_w_5 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_5 | +| ++++Mshreg_gcnt2_w_6 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_6 | +| ++++Mshreg_gcnt2_w_7 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_7 | +| ++++Mshreg_gcnt2_w_8 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_8 | +| ++++Mshreg_gcnt2_w_9 | | 1/1 | 0/0 | 1/1 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/Mshreg_gcnt2_w_9 | +| ++++inst_gray_counter_r | | 20/20 | 23/23 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r | +| ++++inst_gray_counter_w | | 20/20 | 35/35 | 24/24 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_w | +| ++inst_vga_backend | | 60/102 | 24/50 | 62/98 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend | +| +++inst_vga_timing | | 0/42 | 0/26 | 0/36 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing | +| ++++inst_vga_sync_h | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h | +| ++++inst_vga_sync_v | | 21/21 | 13/13 | 18/18 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | mips_sys/inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_v | ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Slices can be packed with basic elements from multiple hierarchies. + Therefore, a slice will be counted in every hierarchical module + that each of its packed basic elements belong to. +** For each column, there are two numbers reported /. + is the number of elements that belong to that specific hierarchical module. + is the total number of elements from that hierarchical module and any lower level + hierarchical modules below. +*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.