jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Minor changes to max cycle count

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@738 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-02-09 09:56:44 +00:00
parent b6dcc8cc48
commit 80dbbd7024
2 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
+3 -3
View File
@@ -57,7 +57,7 @@ architecture behaviour of sdram_cmd is
signal st_sdr, st_sdr_next : sdr_state_t;
signal cc_preset : natural range 0 to 10;
signal cc_preset : natural range 0 to 15;
signal cc_load_en : std_logic;
signal cycle_finished : std_logic;
@@ -65,7 +65,7 @@ architecture behaviour of sdram_cmd is
signal burst_load_en : std_logic;
signal burst_finished : std_logic;
subtype cycle_cnt_t is natural range 0 to 10;
subtype cycle_cnt_t is natural range 0 to 15;
type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t;
constant TIMING : part_timing_array_t :=
@@ -249,7 +249,7 @@ fsm_sdr_state_next:
------------------------------------------------------------------------------------------
cycle_counter:
process (rst, clk)
variable cycle_cnt : natural range 0 to 10;
variable cycle_cnt : natural range 0 to 15;
begin
if rst = '1' then
cycle_cnt := 0;