From 80dbbd702411499ed3369132f970cef113f57150 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 9 Feb 2010 09:56:44 +0000 Subject: [PATCH] Minor changes to max cycle count Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@738 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd | 6 +++--- lib/misc/async_port_wb.vhd | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd index 1834249..ae38d48 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd @@ -57,7 +57,7 @@ architecture behaviour of sdram_cmd is signal st_sdr, st_sdr_next : sdr_state_t; - signal cc_preset : natural range 0 to 10; + signal cc_preset : natural range 0 to 15; signal cc_load_en : std_logic; signal cycle_finished : std_logic; @@ -65,7 +65,7 @@ architecture behaviour of sdram_cmd is signal burst_load_en : std_logic; signal burst_finished : std_logic; - subtype cycle_cnt_t is natural range 0 to 10; + subtype cycle_cnt_t is natural range 0 to 15; type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; constant TIMING : part_timing_array_t := @@ -249,7 +249,7 @@ fsm_sdr_state_next: ------------------------------------------------------------------------------------------ cycle_counter: process (rst, clk) - variable cycle_cnt : natural range 0 to 10; + variable cycle_cnt : natural range 0 to 15; begin if rst = '1' then cycle_cnt := 0; diff --git a/lib/misc/async_port_wb.vhd b/lib/misc/async_port_wb.vhd index 26e0c88..854edd0 100644 --- a/lib/misc/async_port_wb.vhd +++ b/lib/misc/async_port_wb.vhd @@ -1,5 +1,5 @@ ----------------------------------------------------------------------- --- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.15 2010-02-09 07:46:19 Jens Exp $ +-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.16 2010-02-09 09:56:37 Jens Exp $ ----------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; @@ -57,8 +57,8 @@ architecture Behavioral of async_port_wb is signal as : async_t; signal ack : std_logic; signal cc_rst : std_logic; - signal cycle_cnt : natural range 0 to 15; - signal cycle_reload : natural range 0 to 15; + signal cycle_cnt : natural range 0 to 31; + signal cycle_reload : natural range 0 to 31; signal rdy : std_logic; signal rdyo : std_logic; signal en : std_logic;