diff --git a/lib/VGA_ctrl/src/tb_vga_frontend.vhd b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
index 5911dde..01bdf94 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend.vhd
@@ -173,33 +173,62 @@ STIMULUS: process
 		RST_O <= '0';
 		wait for 60*CLK_PERIOD;
 
-		-- 8 single cycles
+		-- Enable master
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_O	<= X"0000_0001";
-		ADDR_O	<= X"0000_0100";
+		SDAT_O	<= X"0000_0002";
+		ADDR_O	<= X"0000_0000";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Read status
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0000";
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read resolution X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0018";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read resolution Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_001C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
 		ADDR_O	<= X"0000_0008";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Read Cursor Y
+		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0000";
-		ADDR_O	<= X"0000_0010";
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Write char 1
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
@@ -208,11 +237,82 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 		
+		-- Read char 1
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Write char 2
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_O	<= X"0000_0035";
-		ADDR_O	<= X"0000_0020";
+		SDAT_O	<= X"0000_0045";
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read char 2
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Set Cursor X
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0012";
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Set Cursor Y
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0014";
+		ADDR_O	<= X"0000_000C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
diff --git a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
index a20242d..55c5cba 100644
--- a/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+++ b/lib/VGA_ctrl/src/tb_vga_frontend64.vhd
@@ -173,33 +173,62 @@ STIMULUS: process
 		RST_O <= '0';
 		wait for 60*CLK_PERIOD;
 
-		-- 8 single cycles
+		-- Enable master
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_O	<= X"0000_0001";
-		ADDR_O	<= X"0000_0100";
+		SDAT_O	<= X"0000_0002";
+		ADDR_O	<= X"0000_0000";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Read status
 		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0000";
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0000";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read resolution X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0018";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read resolution Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_001C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
 		ADDR_O	<= X"0000_0008";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Read Cursor Y
+		CYC_O	<= '1';
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
-		WE_O	<= '1';
-		SDAT_O	<= X"0000_0000";
-		ADDR_O	<= X"0000_0010";
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 
+		-- Write char 1
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
@@ -208,11 +237,82 @@ STIMULUS: process
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';
 		
+		-- Read char 1
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Write char 2
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '1';
 		WE_O	<= '1';
-		SDAT_O	<= X"0000_0035";
-		ADDR_O	<= X"0000_0020";
+		SDAT_O	<= X"0000_0045";
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read char 2
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0004";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Set Cursor X
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0012";
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Set Cursor Y
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '1';
+		SDAT_O	<= X"0000_0014";
+		ADDR_O	<= X"0000_000C";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+		
+		-- Read Cursor X
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_0008";
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '0';
+
+		-- Read Cursor Y
+		CYC_O	<= '1';
+		wait until rising_edge(CLK_O) and SRDY_I = '1';
+		STB_O	<= '1';
+		WE_O	<= '0';
+		ADDR_O	<= X"0000_000C";
 		wait until rising_edge(CLK_O) and SRDY_I = '1';
 		STB_O	<= '0';