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[Uart_wb]

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- fixed: f_sysclk is in MHz

git-svn-id: http://moon:8086/svn/vhdl/trunk@1365 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2017-01-11 08:08:40 +00:00
parent 7f91449b94
commit 652dfe00a2
1 changed files with 2 additions and 2 deletions
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lib/uart/uart_wb.vhd
+2 -2
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@@ -8,7 +8,7 @@ USE WORK.uart_types.all;
ENTITY uart_wb IS ENTITY uart_wb IS
Generic Generic
( (
f_sysclk : real := 100.0e6; f_sysclk : real := 100.0;
baudrate_default : real := 115200.0; baudrate_default : real := 115200.0;
fifo_depth_bits : integer := 4 fifo_depth_bits : integer := 4
); );
@@ -100,7 +100,7 @@ registers_write:
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
reg_we_uart_tx <= '0'; reg_we_uart_tx <= '0';
if RST_I = '1' then if RST_I = '1' then
reg_uart_baud <= to_unsigned(integer(0.5+f_sysclk/(16.0*baudrate_default))-1, 16); reg_uart_baud <= to_unsigned(integer(0.5+f_sysclk*1.0e6/(16.0*baudrate_default))-1, 16);
rx_int_en <= '0'; rx_int_en <= '0';
tx_int_en <= '0'; tx_int_en <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then elsif (STB_I and CYC_I and WE_I) = '1' then